Datasheet ISM330DHCX (STMicroelectronics) - 5
| Fabricante | STMicroelectronics |
| Descripción | iNEMO inertial module with Machine Learning Core |
| Páginas / Página | 167 / 5 — ISM330DHCX. Finite State Machine. 2.1. Definition of Finite State … |
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ISM330DHCX. Finite State Machine. 2.1. Definition of Finite State Machine. Figure 1. Generic state machine
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ISM330DHCX Finite State Machine 2.1 Finite State Machine
The ISM330DHCX can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection and decoding.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop state). The current state is determined by the past states of the system. The following figure shows a generic state machine.
Figure 1. Generic state machine Finite State Machine in the ISM330DHCX
The ISM330DHCX works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature (Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine (Figure 2. State machine in the ISM330DHCX). All 16 finite state machines are independent: each one has its dedicated memory area and it is independently executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the ISM330DHCX
ISM330DHCX ACC [LSB] SIGNAL CONDITIONING FSM FSM Output EXT. SENSOR (MAG) [LSB] (optional)
DS13012
-
Rev 5 page 5/167
Document Outline Features Applications Description 1 Overview 2 Embedded low-power features 2.1 Finite State Machine 2.2 Machine Learning Core 3 Pin description 3.1 Pin connections 4 Module specifications 4.1 Mechanical characteristics 4.2 Electrical characteristics 4.3 Temperature sensor characteristics 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface 4.4.2 I²C - inter-IC control interface 4.5 Absolute maximum ratings 4.6 Terminology 4.6.1 Sensitivity 4.6.2 Zero-g and zero-rate level 5 Digital interfaces 5.1 I²C/SPI interface 5.1.1 I²C serial interface 5.1.1.1 I²C operation 5.1.2 SPI bus interface 5.1.2.1 SPI read 5.1.2.2 SPI write 5.1.2.3 SPI read in 3-wire mode 5.2 Master I²C interface 5.3 Auxiliary SPI interface 6 Functionality 6.1 Operating modes 6.2 Gyroscope power modes 6.3 Accelerometer power modes 6.4 Block diagram of filters 6.4.1 Block diagrams of the accelerometer filters 6.4.2 Block diagrams of the gyroscope filters 6.5 FIFO 6.5.1 Bypass mode 6.5.2 FIFO mode 6.5.3 Continuous mode 6.5.4 Continuous-to-FIFO mode 6.5.5 Bypass-to-Continuous mode 6.5.6 Bypass-to-FIFO mode 6.5.7 FIFO reading procedure 7 Application hints 7.1 ISM330DHCX electrical connections in Mode 1 7.2 ISM330DHCX electrical connections in Mode 2 7.3 ISM330DHCX electrical connections in Mode 3 and Mode 4 8 Register mapping 9 Register description 9.1 FUNC_CFG_ACCESS (01h) 9.2 PIN_CTRL (02h) 9.3 FIFO_CTRL1 (07h) 9.4 FIFO_CTRL2 (08h) 9.5 FIFO_CTRL3 (09h) 9.6 FIFO_CTRL4 (0Ah) 9.7 COUNTER_BDR_REG1 (0Bh) 9.8 COUNTER_BDR_REG2 (0Ch) 9.9 INT1_CTRL (0Dh) 9.10 INT2_CTRL (0Eh) 9.11 WHO_AM_I (0Fh) 9.12 CTRL1_XL (10h) 9.13 CTRL2_G (11h) 9.14 CTRL3_C (12h) 9.15 CTRL4_C (13h) 9.16 CTRL5_C (14h) 9.17 CTRL6_C (15h) 9.18 CTRL7_G (16h) 9.19 CTRL8_XL (17h) 9.20 CTRL9_XL (18h) 9.21 CTRL10_C (19h) 9.22 ALL_INT_SRC (1A) 9.23 WAKE_UP_SRC (1Bh) 9.24 TAP_SRC (1Ch) 9.25 DRD_SRC (1Dh) 9.26 STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) 9.27 OUT_TEMP_L (20h), OUT_TEMP_H (21h) 9.28 OUTX_L_G (22h) and OUTX_H_G (23h) 9.29 OUTY_L_G (24h) and OUTY_H_G (25h) 9.30 OUTZ_L_G (26h) and OUTZ_H_G (27h) 9.31 OUTX_L_A (28h) and OUTX_H_A (29h) 9.32 OUTY_L_A (2Ah) and OUTY_H_A (2Bh) 9.33 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) 9.34 EMB_FUNC_STATUS_MAINPAGE (35h) 9.35 FSM_STATUS_A_MAINPAGE (36h) 9.36 FSM_STATUS_B_MAINPAGE (37h) 9.37 MLC_STATUS_MAINPAGE (38h) 9.38 STATUS_MASTER_MAINPAGE (39h) 9.39 FIFO_STATUS1 (3Ah) 9.40 FIFO_STATUS2 (3Bh) 9.41 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 9.42 TAP_CFG0 (56h) 9.43 TAP_CFG1 (57h) 9.44 TAP_CFG2 (58h) 9.45 TAP_THS_6D (59h) 9.46 INT_DUR2 (5Ah) 9.47 WAKE_UP_THS (5Bh) 9.48 WAKE_UP_DUR (5Ch) 9.49 FREE_FALL (5Dh) 9.50 MD1_CFG (5Eh) 9.51 MD2_CFG (5Fh) 9.52 INTERNAL_FREQ_FINE (63h) 9.53 INT_OIS (6Fh) 9.54 CTRL1_OIS (70h) 9.55 CTRL2_OIS (71h) 9.56 CTRL3_OIS (72h) 9.57 X_OFS_USR (73h) 9.58 Y_OFS_USR (74h) 9.59 Z_OFS_USR (75h) 9.60 FIFO_DATA_OUT_TAG (78h) 9.61 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) 9.62 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) 9.63 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) 10 Embedded functions register mapping 11 Embedded functions register description 11.1 PAGE_SEL (02h) 11.2 EMB_FUNC_EN_A (04h) 11.3 EMB_FUNC_EN_B (05h) 11.4 PAGE_ADDRESS (08h) 11.5 PAGE_VALUE (09h) 11.6 EMB_FUNC_INT1 (0Ah) 11.7 FSM_INT1_A (0Bh) 11.8 FSM_INT1_B (0Ch) 11.9 MLC_INT1 (0Dh) 11.10 EMB_FUNC_INT2 (0Eh) 11.11 FSM_INT2_A (0Fh) 11.12 FSM_INT2_B (10h) 11.13 MLC_INT2 (11h) 11.14 EMB_FUNC_STATUS (12h) 11.15 FSM_STATUS_A (13h) 11.16 FSM_STATUS_B (14h) 11.17 MLC_STATUS (15h) 11.18 PAGE_RW (17h) 11.19 EMB_FUNC_FIFO_CFG (44h) 11.20 FSM_ENABLE_A (46h) 11.21 FSM_ENABLE_B (47h) 11.22 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) 11.23 FSM_LONG_COUNTER_CLEAR (4Ah) 11.24 FSM_OUTS1 (4Ch) 11.25 FSM_OUTS2 (4Dh) 11.26 FSM_OUTS3 (4Eh) 11.27 FSM_OUTS4 (4Fh) 11.28 FSM_OUTS5 (50h) 11.29 FSM_OUTS6 (51h) 11.30 FSM_OUTS7 (52h) 11.31 FSM_OUTS8 (53h) 11.32 FSM_OUTS9 (54h) 11.33 FSM_OUTS10 (55h) 11.34 FSM_OUTS11 (56h) 11.35 FSM_OUTS12 (57h) 11.36 FSM_OUTS13 (58h) 11.37 FSM_OUTS14 (59h) 11.38 FSM_OUTS15 (5Ah) 11.39 FSM_OUTS16 (5Bh) 11.40 EMB_FUNC_ODR_CFG_B (5Fh) 11.41 EMB_FUNC_ODR_CFG_C (60h) 11.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) 11.43 EMB_FUNC_SRC (64h) 11.44 EMB_FUNC_INIT_A (66h) 11.45 EMB_FUNC_INIT_B (67h) 11.46 MLC0_SRC (70h) 11.47 MLC1_SRC (71h) 11.48 MLC2_SRC (72h) 11.49 MLC3_SRC (73h) 11.50 MLC4_SRC (74h) 11.51 MLC5_SRC (75h) 11.52 MLC6_SRC (76h) 11.53 MLC7_SRC (77h) 12 Embedded advanced features pages 13 Embedded advanced features register description 13.1 Page 0 - Embedded advanced features registers 13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) 13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h) 13.1.3 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h) 13.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) 13.1.5 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) 13.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) 13.1.7 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) 13.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) 13.1.9 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) 13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) 13.1.11 MAG_CFG_A (D4h) 13.1.12 MAG_CFG_B (D5h) 13.2 Page 1 - Embedded advanced features registers 13.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh) 13.2.2 FSM_PROGRAMS (7Ch) 13.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) 13.2.4 PEDO_CMD_REG (83h) 13.2.5 PEDO_DEB_CONF (84h) 13.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) 13.2.7 MLC_MAG_SENSITIVITY_L (E8h) and MLC_MAG_SENSITIVITY_H (E9h) 14 Sensor hub register mapping 15 Sensor hub register description 15.1 SENSOR_HUB_1 (02h) 15.2 SENSOR_HUB_2 (03h) 15.3 SENSOR_HUB_3 (04h) 15.4 SENSOR_HUB_4 (05h) 15.5 SENSOR_HUB_5 (06h) 15.6 SENSOR_HUB_6 (07h) 15.7 SENSOR_HUB_7 (08h) 15.8 SENSOR_HUB_8 (09h) 15.9 SENSOR_HUB_9 (0Ah) 15.10 SENSOR_HUB_10 (0Bh) 15.11 SENSOR_HUB_11 (0Ch) 15.12 SENSOR_HUB_12 (0Dh) 15.13 SENSOR_HUB_13 (0Eh) 15.14 SENSOR_HUB_14 (0Fh) 15.15 SENSOR_HUB_15 (10h) 15.16 SENSOR_HUB_16 (11h) 15.17 SENSOR_HUB_17 (12h) 15.18 SENSOR_HUB_18 (13h) 15.19 MASTER_CONFIG (14h) 15.20 SLV0_ADD (15h) 15.21 SLV0_SUBADD (16h) 15.22 SLAVE0_CONFIG (17h) 15.23 SLV1_ADD (18h) 15.24 SLV1_SUBADD (19h) 15.25 SLAVE1_CONFIG (1Ah) 15.26 SLV2_ADD (1Bh) 15.27 SLV2_SUBADD (1Ch) 15.28 SLAVE2_CONFIG (1Dh) 15.29 SLV3_ADD (1Eh) 15.30 SLV3_SUBADD (1Fh) 15.31 SLAVE3_CONFIG (20h) 15.32 DATAWRITE_SLV0 (21h) 15.33 STATUS_MASTER (22h) 16 Soldering information 17 Package information 17.1 LGA-14L package information 17.2 LGA-14 packing information Revision history Contents List of tables List of figures
ISM330DHCX Finite State Machine 2.1 Finite State Machine
The ISM330DHCX can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection and decoding.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop state). The current state is determined by the past states of the system. The following figure shows a generic state machine.
Figure 1. Generic state machine Finite State Machine in the ISM330DHCX
The ISM330DHCX works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature (Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine (Figure 2. State machine in the ISM330DHCX). All 16 finite state machines are independent: each one has its dedicated memory area and it is independently executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the ISM330DHCX
ISM330DHCX ACC [LSB] SIGNAL CONDITIONING FSM FSM Output EXT. SENSOR (MAG) [LSB] (optional)
DS13012
-
Rev 5 page 5/167
Document Outline Features Applications Description 1 Overview 2 Embedded low-power features 2.1 Finite State Machine 2.2 Machine Learning Core 3 Pin description 3.1 Pin connections 4 Module specifications 4.1 Mechanical characteristics 4.2 Electrical characteristics 4.3 Temperature sensor characteristics 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface 4.4.2 I²C - inter-IC control interface 4.5 Absolute maximum ratings 4.6 Terminology 4.6.1 Sensitivity 4.6.2 Zero-g and zero-rate level 5 Digital interfaces 5.1 I²C/SPI interface 5.1.1 I²C serial interface 5.1.1.1 I²C operation 5.1.2 SPI bus interface 5.1.2.1 SPI read 5.1.2.2 SPI write 5.1.2.3 SPI read in 3-wire mode 5.2 Master I²C interface 5.3 Auxiliary SPI interface 6 Functionality 6.1 Operating modes 6.2 Gyroscope power modes 6.3 Accelerometer power modes 6.4 Block diagram of filters 6.4.1 Block diagrams of the accelerometer filters 6.4.2 Block diagrams of the gyroscope filters 6.5 FIFO 6.5.1 Bypass mode 6.5.2 FIFO mode 6.5.3 Continuous mode 6.5.4 Continuous-to-FIFO mode 6.5.5 Bypass-to-Continuous mode 6.5.6 Bypass-to-FIFO mode 6.5.7 FIFO reading procedure 7 Application hints 7.1 ISM330DHCX electrical connections in Mode 1 7.2 ISM330DHCX electrical connections in Mode 2 7.3 ISM330DHCX electrical connections in Mode 3 and Mode 4 8 Register mapping 9 Register description 9.1 FUNC_CFG_ACCESS (01h) 9.2 PIN_CTRL (02h) 9.3 FIFO_CTRL1 (07h) 9.4 FIFO_CTRL2 (08h) 9.5 FIFO_CTRL3 (09h) 9.6 FIFO_CTRL4 (0Ah) 9.7 COUNTER_BDR_REG1 (0Bh) 9.8 COUNTER_BDR_REG2 (0Ch) 9.9 INT1_CTRL (0Dh) 9.10 INT2_CTRL (0Eh) 9.11 WHO_AM_I (0Fh) 9.12 CTRL1_XL (10h) 9.13 CTRL2_G (11h) 9.14 CTRL3_C (12h) 9.15 CTRL4_C (13h) 9.16 CTRL5_C (14h) 9.17 CTRL6_C (15h) 9.18 CTRL7_G (16h) 9.19 CTRL8_XL (17h) 9.20 CTRL9_XL (18h) 9.21 CTRL10_C (19h) 9.22 ALL_INT_SRC (1A) 9.23 WAKE_UP_SRC (1Bh) 9.24 TAP_SRC (1Ch) 9.25 DRD_SRC (1Dh) 9.26 STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) 9.27 OUT_TEMP_L (20h), OUT_TEMP_H (21h) 9.28 OUTX_L_G (22h) and OUTX_H_G (23h) 9.29 OUTY_L_G (24h) and OUTY_H_G (25h) 9.30 OUTZ_L_G (26h) and OUTZ_H_G (27h) 9.31 OUTX_L_A (28h) and OUTX_H_A (29h) 9.32 OUTY_L_A (2Ah) and OUTY_H_A (2Bh) 9.33 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) 9.34 EMB_FUNC_STATUS_MAINPAGE (35h) 9.35 FSM_STATUS_A_MAINPAGE (36h) 9.36 FSM_STATUS_B_MAINPAGE (37h) 9.37 MLC_STATUS_MAINPAGE (38h) 9.38 STATUS_MASTER_MAINPAGE (39h) 9.39 FIFO_STATUS1 (3Ah) 9.40 FIFO_STATUS2 (3Bh) 9.41 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 9.42 TAP_CFG0 (56h) 9.43 TAP_CFG1 (57h) 9.44 TAP_CFG2 (58h) 9.45 TAP_THS_6D (59h) 9.46 INT_DUR2 (5Ah) 9.47 WAKE_UP_THS (5Bh) 9.48 WAKE_UP_DUR (5Ch) 9.49 FREE_FALL (5Dh) 9.50 MD1_CFG (5Eh) 9.51 MD2_CFG (5Fh) 9.52 INTERNAL_FREQ_FINE (63h) 9.53 INT_OIS (6Fh) 9.54 CTRL1_OIS (70h) 9.55 CTRL2_OIS (71h) 9.56 CTRL3_OIS (72h) 9.57 X_OFS_USR (73h) 9.58 Y_OFS_USR (74h) 9.59 Z_OFS_USR (75h) 9.60 FIFO_DATA_OUT_TAG (78h) 9.61 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) 9.62 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) 9.63 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) 10 Embedded functions register mapping 11 Embedded functions register description 11.1 PAGE_SEL (02h) 11.2 EMB_FUNC_EN_A (04h) 11.3 EMB_FUNC_EN_B (05h) 11.4 PAGE_ADDRESS (08h) 11.5 PAGE_VALUE (09h) 11.6 EMB_FUNC_INT1 (0Ah) 11.7 FSM_INT1_A (0Bh) 11.8 FSM_INT1_B (0Ch) 11.9 MLC_INT1 (0Dh) 11.10 EMB_FUNC_INT2 (0Eh) 11.11 FSM_INT2_A (0Fh) 11.12 FSM_INT2_B (10h) 11.13 MLC_INT2 (11h) 11.14 EMB_FUNC_STATUS (12h) 11.15 FSM_STATUS_A (13h) 11.16 FSM_STATUS_B (14h) 11.17 MLC_STATUS (15h) 11.18 PAGE_RW (17h) 11.19 EMB_FUNC_FIFO_CFG (44h) 11.20 FSM_ENABLE_A (46h) 11.21 FSM_ENABLE_B (47h) 11.22 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) 11.23 FSM_LONG_COUNTER_CLEAR (4Ah) 11.24 FSM_OUTS1 (4Ch) 11.25 FSM_OUTS2 (4Dh) 11.26 FSM_OUTS3 (4Eh) 11.27 FSM_OUTS4 (4Fh) 11.28 FSM_OUTS5 (50h) 11.29 FSM_OUTS6 (51h) 11.30 FSM_OUTS7 (52h) 11.31 FSM_OUTS8 (53h) 11.32 FSM_OUTS9 (54h) 11.33 FSM_OUTS10 (55h) 11.34 FSM_OUTS11 (56h) 11.35 FSM_OUTS12 (57h) 11.36 FSM_OUTS13 (58h) 11.37 FSM_OUTS14 (59h) 11.38 FSM_OUTS15 (5Ah) 11.39 FSM_OUTS16 (5Bh) 11.40 EMB_FUNC_ODR_CFG_B (5Fh) 11.41 EMB_FUNC_ODR_CFG_C (60h) 11.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) 11.43 EMB_FUNC_SRC (64h) 11.44 EMB_FUNC_INIT_A (66h) 11.45 EMB_FUNC_INIT_B (67h) 11.46 MLC0_SRC (70h) 11.47 MLC1_SRC (71h) 11.48 MLC2_SRC (72h) 11.49 MLC3_SRC (73h) 11.50 MLC4_SRC (74h) 11.51 MLC5_SRC (75h) 11.52 MLC6_SRC (76h) 11.53 MLC7_SRC (77h) 12 Embedded advanced features pages 13 Embedded advanced features register description 13.1 Page 0 - Embedded advanced features registers 13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) 13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h) 13.1.3 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h) 13.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) 13.1.5 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) 13.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) 13.1.7 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) 13.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) 13.1.9 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) 13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) 13.1.11 MAG_CFG_A (D4h) 13.1.12 MAG_CFG_B (D5h) 13.2 Page 1 - Embedded advanced features registers 13.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh) 13.2.2 FSM_PROGRAMS (7Ch) 13.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) 13.2.4 PEDO_CMD_REG (83h) 13.2.5 PEDO_DEB_CONF (84h) 13.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) 13.2.7 MLC_MAG_SENSITIVITY_L (E8h) and MLC_MAG_SENSITIVITY_H (E9h) 14 Sensor hub register mapping 15 Sensor hub register description 15.1 SENSOR_HUB_1 (02h) 15.2 SENSOR_HUB_2 (03h) 15.3 SENSOR_HUB_3 (04h) 15.4 SENSOR_HUB_4 (05h) 15.5 SENSOR_HUB_5 (06h) 15.6 SENSOR_HUB_6 (07h) 15.7 SENSOR_HUB_7 (08h) 15.8 SENSOR_HUB_8 (09h) 15.9 SENSOR_HUB_9 (0Ah) 15.10 SENSOR_HUB_10 (0Bh) 15.11 SENSOR_HUB_11 (0Ch) 15.12 SENSOR_HUB_12 (0Dh) 15.13 SENSOR_HUB_13 (0Eh) 15.14 SENSOR_HUB_14 (0Fh) 15.15 SENSOR_HUB_15 (10h) 15.16 SENSOR_HUB_16 (11h) 15.17 SENSOR_HUB_17 (12h) 15.18 SENSOR_HUB_18 (13h) 15.19 MASTER_CONFIG (14h) 15.20 SLV0_ADD (15h) 15.21 SLV0_SUBADD (16h) 15.22 SLAVE0_CONFIG (17h) 15.23 SLV1_ADD (18h) 15.24 SLV1_SUBADD (19h) 15.25 SLAVE1_CONFIG (1Ah) 15.26 SLV2_ADD (1Bh) 15.27 SLV2_SUBADD (1Ch) 15.28 SLAVE2_CONFIG (1Dh) 15.29 SLV3_ADD (1Eh) 15.30 SLV3_SUBADD (1Fh) 15.31 SLAVE3_CONFIG (20h) 15.32 DATAWRITE_SLV0 (21h) 15.33 STATUS_MASTER (22h) 16 Soldering information 17 Package information 17.1 LGA-14L package information 17.2 LGA-14 packing information Revision history Contents List of tables List of figures