Datasheet 8V97003 (IDT) - 5

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List of Figures
Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package ― Top View ... 8 Figure 2. Phase Noise at 6GHz (Fractional Mode).. 18 Figure 3. Phase Noise at 6GHz (Integer Mode) .. 18 Figure 4. Phase Noise at 8GHz (Integer Mode) .. 19 Figure 5. Phase Noise at 11GHz (Integer Mode) .. 19 Figure 6. Phase Noise at 18GHz (Integer Mode) .. 20 Figure 7. Phase Noise at 8GHz (Open Loop).. 20 Figure 8. Typical Output Power vs. RF Output Frequency (Over Different Loads).. 21 Figure 9. Input Reference Path.. 22 Figure 10. RF Feedback N Divider .. 23 Figure 11. Simplified PFD Circuit using D-type Flip-Flop. ... 24 Figure 12. Output Clock Distribution ... 25 Figure 13. Output Stage .. 26 Figure 14. Resistive Matching Termination .. 26 Figure 15. Inductively Loaded Termination ... 27 Figure 16. 4-Wire MSB First, Single Byte Write and Read .. 30 Figure 17. 4-Wire LSB First, Single Byte Write and Read ... 31 Figure 18. 4-Wire MSB First, Multiple Bytes Write (2 Bytes Shown as Example) ... 31 Figure 19. 4-Wire LSB First, Multiple Bytes Read (2 Bytes Shown as Example) .. 32 Figure 20. 3-Wire MSB First, Single Byte Read and Write .. 32 Figure 21. SPI Timing Diagram . ... 33 Figure 22. Typical 2nd Order Loop Filter.. 56 Figure 23. Typical 3rd Order Loop Filter ... 58 Figure 24. Loop Filter Example.. 58 Figure 25. Schematic Example.. 60 ©2020 Renesas Electronics Corporation 5 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History