Datasheet LTC6993-1, LTC6993-2, LTC6993-3, LTC6993-4 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | TimerBlox: Monostable Pulse Generator (One Shot) |
| Páginas / Página | 28 / 10 — PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):. DIV (Pin 2/Pin 4):. TRIG (Pin … |
| Revisión | E |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):. DIV (Pin 2/Pin 4):. TRIG (Pin 4/Pin 1):. SET (Pin 3/Pin 3):. GND (Pin 5/Pin 2):
Línea de modelo para esta hoja de datos
- LTC6993CDCB-1#TRMPBF LTC6993CDCB-1#TRPBF LTC6993CDCB-2#TRMPBF LTC6993CDCB-2#TRPBF LTC6993CDCB-3#TRMPBF LTC6993CDCB-3#TRPBF LTC6993CDCB-4#TRMPBF LTC6993CDCB-4#TRPBF LTC6993CS6-1#TRMPBF LTC6993CS6-1#TRPBF LTC6993CS6-2#TRMPBF LTC6993CS6-2#TRPBF LTC6993CS6-3#TRMPBF LTC6993CS6-3#TRPBF LTC6993CS6-4#TRMPBF LTC6993CS6-4#TRPBF LTC6993HDCB-1#TRMPBF LTC6993HDCB-1#TRPBF LTC6993HDCB-2#TRMPBF LTC6993HDCB-2#TRPBF LTC6993HDCB-3#TRMPBF LTC6993HDCB-3#TRPBF LTC6993HDCB-4#TRMPBF LTC6993HDCB-4#TRPBF LTC6993HS6-1#TRMPBF LTC6993HS6-1#TRPBF LTC6993HS6-1#WTRMPBF LTC6993HS6-1#WTRPBF LTC6993HS6-2#TRMPBF LTC6993HS6-2#TRPBF LTC6993HS6-2#WTRMPBF LTC6993HS6-2#WTRPBF LTC6993HS6-3#TRMPBF LTC6993HS6-3#TRPBF LTC6993HS6-3#WTRMPBF LTC6993HS6-3#WTRPBF LTC6993HS6-4#TRMPBF LTC6993HS6-4#TRPBF LTC6993HS6-4#WTRMPBF LTC6993HS6-4#WTRPBF LTC6993IDCB-1#TRMPBF LTC6993IDCB-1#TRPBF LTC6993IDCB-2#TRMPBF LTC6993IDCB-2#TRPBF LTC6993IDCB-3#TRMPBF LTC6993IDCB-3#TRPBF LTC6993IDCB-4#TRMPBF LTC6993IDCB-4#TRPBF LTC6993IS6-1#TRMPBF LTC6993IS6-1#TRPBF LTC6993IS6-1#WTRMPBF LTC6993IS6-1#WTRPBF LTC6993IS6-2#TRMPBF LTC6993IS6-2#TRPBF LTC6993IS6-2#WTRMPBF LTC6993IS6-2#WTRPBF LTC6993IS6-3#TRMPBF LTC6993IS6-3#TRPBF LTC6993IS6-3#WTRMPBF LTC6993IS6-3#WTRPBF LTC6993IS6-4#TRMPBF LTC6993IS6-4#TRPBF LTC6993IS6-4#WTRMPBF LTC6993IS6-4#WTRPBF LTC6993MPS6-1#TRMPBF LTC6993MPS6-1#TRPBF LTC6993MPS6-2#TRMPBF LTC6993MPS6-2#TRPBF LTC6993MPS6-3#TRMPBF LTC6993MPS6-3#TRPBF LTC6993MPS6-4#TRMPBF LTC6993MPS6-4#TRPBF
Versión de texto del documento
LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4
PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):
Supply Voltage (2.25V to 5.5V). This tolerance and 50ppm/°C or better temperature coefficient. supply should be kept free from noise and ripple. It should For lower accuracy applications an inexpensive 1% thick be bypassed directly to the GND pin with a 0.1µF capacitor. film resistor may be used.
DIV (Pin 2/Pin 4):
Programmable Divider and Polarity Limit the capacitance on the SET pin to less than 10pF Input. The DIV pin voltage (VDIV) is internally converted to minimize jitter and ensure stability. Capacitance less into a 4-bit result (DIVCODE). VDIV may be generated by than 100pF maintains the stability of the feedback circuit a resistor divider between V+ and GND. Use 1% resistors regulating the VSET voltage. to ensure an accurate result. The DIV pin and resistors
TRIG (Pin 4/Pin 1):
Trigger Input. Depending on the ver- should be shielded from the OUT pin or any other traces sion, a rising or falling edge on TRIG will initiate the output that have fast edges. Limit the capacitance on the DIV pin pulse. LTC6993-1 and LTC6993-2 are rising-edge sensi- to less than 100pF so that VDIV settles quickly. The MSB of tive. LTC6993-3 and LTC6993-4 are fal ing-edge sensitive. DIVCODE (POL) determines the polarity of the OUT pins. When POL = 0 the output produces a positive pulse. When The LTC6993-2 and LTC6993-4 are retriggerable, allowing POL = 1 the output produces a negative pulse. the pulse width to be extended by additional trigger signals that occur while the output is active. The LTC6993-1/
SET (Pin 3/Pin 3):
Pulse Width Setting Input. The voltage LTC6993-3 will ignore additional trigger inputs until the on the SET pin (VSET) is regulated to 1V above GND. The output pulse has terminated. amount of current sourced from the SET pin (ISET) pro- grams the master oscillator frequency. The I
GND (Pin 5/Pin 2):
Ground. Tie to a low inductance ground SET current range is 1.25µA to 20µA. The output pulse will continue plane for best performance. indefinitely if ISET drops below approximately 500nA,
OUT (Pin 6/Pin 6):
Output. The OUT pin swings from and will terminate when ISET increases again. A resistor GND to V+ with an output resistance of approximately connected between SET and GND is the most accurate 30Ω. When driving an LED or other low impedance load way to set the pulse width. For best performance, use a series output resistor should be used to limit source/ a precision metal or thin film resistor of 0.5% or better sink current to 20mA. V+ TRIG OUT LTC6993 V+ GND V+ C1 0.1µF R1 SET DIV 69931234 PF RSET R2 Rev. E 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):
Supply Voltage (2.25V to 5.5V). This tolerance and 50ppm/°C or better temperature coefficient. supply should be kept free from noise and ripple. It should For lower accuracy applications an inexpensive 1% thick be bypassed directly to the GND pin with a 0.1µF capacitor. film resistor may be used.
DIV (Pin 2/Pin 4):
Programmable Divider and Polarity Limit the capacitance on the SET pin to less than 10pF Input. The DIV pin voltage (VDIV) is internally converted to minimize jitter and ensure stability. Capacitance less into a 4-bit result (DIVCODE). VDIV may be generated by than 100pF maintains the stability of the feedback circuit a resistor divider between V+ and GND. Use 1% resistors regulating the VSET voltage. to ensure an accurate result. The DIV pin and resistors
TRIG (Pin 4/Pin 1):
Trigger Input. Depending on the ver- should be shielded from the OUT pin or any other traces sion, a rising or falling edge on TRIG will initiate the output that have fast edges. Limit the capacitance on the DIV pin pulse. LTC6993-1 and LTC6993-2 are rising-edge sensi- to less than 100pF so that VDIV settles quickly. The MSB of tive. LTC6993-3 and LTC6993-4 are fal ing-edge sensitive. DIVCODE (POL) determines the polarity of the OUT pins. When POL = 0 the output produces a positive pulse. When The LTC6993-2 and LTC6993-4 are retriggerable, allowing POL = 1 the output produces a negative pulse. the pulse width to be extended by additional trigger signals that occur while the output is active. The LTC6993-1/
SET (Pin 3/Pin 3):
Pulse Width Setting Input. The voltage LTC6993-3 will ignore additional trigger inputs until the on the SET pin (VSET) is regulated to 1V above GND. The output pulse has terminated. amount of current sourced from the SET pin (ISET) pro- grams the master oscillator frequency. The I
GND (Pin 5/Pin 2):
Ground. Tie to a low inductance ground SET current range is 1.25µA to 20µA. The output pulse will continue plane for best performance. indefinitely if ISET drops below approximately 500nA,
OUT (Pin 6/Pin 6):
Output. The OUT pin swings from and will terminate when ISET increases again. A resistor GND to V+ with an output resistance of approximately connected between SET and GND is the most accurate 30Ω. When driving an LED or other low impedance load way to set the pulse width. For best performance, use a series output resistor should be used to limit source/ a precision metal or thin film resistor of 0.5% or better sink current to 20mA. V+ TRIG OUT LTC6993 V+ GND V+ C1 0.1µF R1 SET DIV 69931234 PF RSET R2 Rev. E 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts