Datasheet ADT7470 (Analog Devices) - 9

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Data Sheet ADT7470 SMBUS/I2C SERIAL INTERFACE 1 16
Control of the ADT7470 is carried out using the serial system
2 15
management bus (SMBus). This interface is fully compatible
3 ADT7470 14
with SMBus 2.0 electrical specifications and meets 400 pF bus
4 13
capacitance requirements. The device also supports fast I2C
5 12
(400 kHz max). The ADT7470 is connected to the bus as a slave
ADDR 6 11
device under the control of a master control er or service
7 10
processor.
8 9 ADDRESS SELECTION
04684-0-006 The ADT7470 has a 7-bit serial bus address. When the device Figure 6. SMBus Address = 0x5C or 0x2E (Pin 11 = Floating) is powered up with Pin 11 (ADDR) high, the ADT7470 has an The device address is sampled and latched on the first valid SMBus address of 010 1111 or 0x5E (left-justified). Because the SMBus transaction, so any additional attempted addressing address is 7 bits, it can be left- or right-justified; this determines changes have no immediate effect. The facility to make whether the address reads as 0x5x or 0x2x. Pin 11 can be left hardwired changes to the SMBus slave address allows the user floating or tied low for other addressing options, as shown in to avoid conflicts with other devices sharing the same serial bus, Table 5. See also Figure 4, Figure 5, and Figure 6. for example, if more than one ADT7470 is used in a system.
Table 5. ADT7470 Address Select Mode SERIAL BUS PROTOCOL Pin 11 (ADDR) State Address
The serial bus protocol operates as follows: High (10 kΩ to VCC) 010 1111 (0x5E left-justified or 1. The master initiates data transfer by establishing a start 0x2F right-justified) condition, defined as a high-to-low transition on the serial Low (10 kΩ to GND) 010 1100 (0x58 left-justified or 0x2C right-justified) data line, SDA, while the serial clock line, SCL, remains Floating (no pull-up) 010 1110 (0x5C left-justified or high. This indicates that an address/data stream fol ows. 0x2E right-justified) All slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consist- ing of a 7-bit address (MSB first) and an R/W bit. This determines the direction of the data transfer, that is,
1 16
whether data is written to or read from the slave device.
2 15
The peripheral whose address corresponds to the transmit-
3 ADT7470 14 VCC
ted address responds by pulling the data line low during
4 13
the low period before the 9th clock pulse, known as the
12 10k
Ω
5 TYP
acknowledge bit. All other devices on the bus now remain
ADDR 6 11
idle while the selected device waits for data to be read from
7 10
or written to it. If the R/W bit is 0, the master writes to the
8 9
slave device. If the R/W bit is 1, the master reads from the 04684-0-004 slave device. Figure 4. SMBus Address = 0x5E or 0x2F (Pin 11 = 1) 2. Data is sent over the serial bus in sequences of 9 clock pulses: 8 bits of data followed by an acknowledge bit from the slave
1 16
device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the
2 15
high period. This is because a low-to-high transition when
3 ADT7470 14
the clock is high might be interpreted as a stop signal. The
4 13
number of data bytes that can be transmitted over the serial
5 12
bus in a single read or write operation is limited only by
ADDR 6 11
what the master and slave devices can handle.
7 10 10k
Ω 3. After all data bytes are read or written, stop conditions
TYP 8 9
are established. In write mode, the master pul s the data 04684-0-005 line high during the 10th clock pulse to assert a stop Figure 5. SMBus Address = 0x58 or 0x2C (Pin 11 = 0) condition. In read mode, the master device overrides the acknowledge bit by pul ing the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master then takes the data line low Rev. E | Page 9 of 40 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Serial Bus Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Functional Description General Description ADT7470 Monitoring Cycle Configuration Register 1 (Address 0x40) Configuration Register 2 (Address 0x74) ID Registers General-Purpose I/O Pins (Open Drain) SMBus/I2C Serial Interface Address Selection Serial Bus Protocol Write Operations Send Byte Write Byte Read Operations Receive Byte Alert Response Address SMBus Timeout Temperature Measurement Using TMP05/TMP06 Measuring Temperature TMP05/TMP06 Decoder Temperature ReadBack By the Host Temperature Data Format Temperature Measurement Limits Thermal Zones for Automatic Fan Control Thermal Zone TMIN Limit and Status Registers Limit Values Temperature Limits Fan Speed Limits Out-of-Limit Comparisons Status Registers SMBALERT Interrupt Handling SMBALERT Interrupts Masking Interrupt Sources Enabling the SMBALERT Interrupt Output Fan Drive Using PWM Control High Frequency Fan Drive Low Frequency Fan Drive Setting the Fan Drive Frequency Inverted PWM Output Fan Full Speed Function Fan Speed Measurement Tach Inputs Pulse Stretching Disabling Tach measurement Fan Speed Measurement Fan Speed Measurement Registers Reading Fan Speed from the ADT7470 Fan Tach Limit Registers Fan Speed Measurement Rate Calculating Fan Speed and Tachometer Limits Fan Pulses per Revolution Manual Fan Speed Control Setting the PWM Duty Cycle Example 1: For a PWM Duty Cycle of 50% Example 2: For a PWM Duty Cycle of 33% Automatic Fan Speed Control PWM Min Duty Cycle Example: For a PWM Min Duty Cycle of 30% PWN Max Duty Cycle PWM Current Duty Cycle Register Map Detailed Register Descriptions Outline Dimensions Ordering Guide