Datasheet ADT75 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | ±1°C Accurate, 12-Bit Digital Temperature Sensor |
| Páginas / Página | 24 / 6 — ADT75. Data Sheet. TIMING SPECIFICATIONS AND DIAGRAM. Table 3. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 353 Kb |
| Idioma del documento | Inglés |
ADT75. Data Sheet. TIMING SPECIFICATIONS AND DIAGRAM. Table 3. Parameter1. Min. Typ. Max. Unit. Test Conditions/Comments. SCL. SDA. DATA IN
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ADT75 Data Sheet TIMING SPECIFICATIONS AND DIAGRAM
Measure the SDA and SCL timing with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted.
Table 3. Parameter1 Min Typ Max Unit Test Conditions/Comments
Serial Clock Period, t 2.5 µs Fast mode I2C. See Figure 2 1 Data In Setup Time to SCL High, t 50 ns See Figure 2 2 Data Out Stable After SCL Low, t 0 0.92 ns Fast mode I2C. See Figure 2 3 Data Out Stable After SCL Low, t 0 3.452 µs Standard mode I2C. See Figure 2 3 SDA Low Setup Time to SCL Low (Start Condition), t 50 ns See Figure 2 4 SDA High Hold Time After SCL High (Stop Condition), t 50 ns See Figure 2 5 SDA and SCL Rise Time, t 300 ns Fast mode I2C. See Figure 2 6 SDA and SCL Rise Time, t 1000 ns Standard mode I2C. See Figure 2 6 SDA and SCL Fall Time, t 300 ns See Figure 2 7 Capacitive Load for each Bus Line, C 400 pF B 1 Guaranteed by design and characterization; not production tested. 2 This time has to be met only if the master does not stretch the low period of the SCL signal.
t1 SCL t t t 2 5 4 SDA DATA IN t3 SDA DATA OUT t7 t6
05326-002 Figure 2. SMBus/I2C Timing Diagram Rev. B | Page 6 of 24 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications A Grade B Grade Timing Specifications and Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Information Converter Details Functional Description Temperature Data Format Temperature Conversion Formulas One-Shot Mode Fault Queue Registers Address Pointer Register Temperature Value Register Configuration Register THYST Setpoint Register TOS Setpoint Register Serial Interface Serial Bus Address Writing Data Writing to the Address Pointer Register for a Subsequent Read Writing Data to a Register Reading Data OS/Alert Output OverTemperature Modes Comparator Mode Interrupt Mode SMBus Alert Applications Information Thermal Response Time Self-Heating Effects Supply Decoupling Temperature Monitoring Outline Dimensions Ordering Guide
ADT75 Data Sheet TIMING SPECIFICATIONS AND DIAGRAM
Measure the SDA and SCL timing with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted.
Table 3. Parameter1 Min Typ Max Unit Test Conditions/Comments
Serial Clock Period, t 2.5 µs Fast mode I2C. See Figure 2 1 Data In Setup Time to SCL High, t 50 ns See Figure 2 2 Data Out Stable After SCL Low, t 0 0.92 ns Fast mode I2C. See Figure 2 3 Data Out Stable After SCL Low, t 0 3.452 µs Standard mode I2C. See Figure 2 3 SDA Low Setup Time to SCL Low (Start Condition), t 50 ns See Figure 2 4 SDA High Hold Time After SCL High (Stop Condition), t 50 ns See Figure 2 5 SDA and SCL Rise Time, t 300 ns Fast mode I2C. See Figure 2 6 SDA and SCL Rise Time, t 1000 ns Standard mode I2C. See Figure 2 6 SDA and SCL Fall Time, t 300 ns See Figure 2 7 Capacitive Load for each Bus Line, C 400 pF B 1 Guaranteed by design and characterization; not production tested. 2 This time has to be met only if the master does not stretch the low period of the SCL signal.
t1 SCL t t t 2 5 4 SDA DATA IN t3 SDA DATA OUT t7 t6
05326-002 Figure 2. SMBus/I2C Timing Diagram Rev. B | Page 6 of 24 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications A Grade B Grade Timing Specifications and Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Information Converter Details Functional Description Temperature Data Format Temperature Conversion Formulas One-Shot Mode Fault Queue Registers Address Pointer Register Temperature Value Register Configuration Register THYST Setpoint Register TOS Setpoint Register Serial Interface Serial Bus Address Writing Data Writing to the Address Pointer Register for a Subsequent Read Writing Data to a Register Reading Data OS/Alert Output OverTemperature Modes Comparator Mode Interrupt Mode SMBus Alert Applications Information Thermal Response Time Self-Heating Effects Supply Decoupling Temperature Monitoring Outline Dimensions Ordering Guide