Datasheet IR3889 IR OptiMOS IPOL (Infineon) - 7

IR OptiMOS™ IPOL 30 A single-voltage synchronous Buck regulator Pin descriptions 4 Pin descriptions
Note: I = Input, O = Output
Pin# Pin Name I/O Type Pin Description
Connecting a resistor to a quiet ground to set the Over 1 ILIM I Analog Current Protection (OCP) limit. Four user selectable OCP limits are available. Power Good status output pin is open drain. Connect a pull 2 PGood O Analog up resistor from this pin to VCC or to an external bias voltage, e.g. 3.3 V. Input voltage for an Internal LDO. A 4.7 µF capacitor should be connected between this pin and PGND. If an external 3 Vin I Power supply is connected to VCC/LDO pin, this pin should be shorted to VCC/LDO pin and a 10 µF ceramic capacitor can be shared with Vin and VCC/LDO pin. Output of the internal LDO or input for an external VCC 4 VCC/LDO I/O Power voltage. A 2.2 µF - 10 µF ceramic capacitor is recommended to use between VCC, VDRV and the Power ground (PGND). Input bias for the internal driver. It should be shorted to VCC/LDO pin on the PCB. A 2.2 µF - 10 µF ceramic capacitor is 5 VDRV I Power recommended to use between VDRV, VCC/LDO and the Power ground (PGND). Gate of Low-side FET. This pin can be used to monitor the 6, 37 GATEL I Analog gate signal of LS FET. No external components should be connected to it. Power Ground. Must be connected to the system’s power 7, 8, 9, 10, PGND - Ground ground plane. PGND and AGND are internally connected via 19 the lead frame. 11, 12, 13, 14, 15, 16, SW O Power Switch Node. Connect these pins to an output inductor. 17, 18 20, 21, 22, PVin I Power Input supply for the power stage. 23, 24 Source of High-side FET. Connect a bootstrap capacitor 25 PHASE O Analog between this pin and BOOT pin. A high temperature (x7R) 0.1 µF or greater value ceramic capacitor is recommended. Supply voltage for the high side driver. Connect this pin to the PHASE pin through a bootstrap capacitor. For PVin above 26 BOOT I Analog 14 V, a resistor (e.g., 1 Ω~ Ω is recommended in series with the bootstrap capacitor to control the slew rate of the SW node rising edge. 27 En I Analog Enable pin to turn the IC on and off. Multi-function pin. Connect a resistor to a quiet ground to select Soft-Start time from 4 options. This pin also selects 29 SS/Latch I Analog latched-off Over Voltage Protection (OVP) or non-latched OVP. Final Datasheet 7 of 50 V2.4 2020-1-16 Document Outline Revision History Trademarks Disclaimer