Datasheet ACS37612 (Allegro) - 5

Coreless, High Precision, Hall-Effect Current Sensor IC ACS37612 with Common-Mode Field Rejection and High Bandwidth (240 kHz) COMMON OPERATING CHARACTERISTICS:
Valid at TOP = –40°C to 150°C and VCC = 5 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS
Hall Spacing HDIST Distance between Halls – 1.87 – mm 5 V nominal supply voltage variant 4.5 5 5.5 V Supply Voltage VCC 3.3 V nominal supply voltage variant 3 3.3 3.6 V Supply Current I VCC(min) ≤ VCC ≤ VCC(max), where VCC = 5 V or 3.3 V, CC no load on output – 12 16 mA Power-On Delay tPO TA = 25°C – 70 – µs Temperature Compensation Power-On Time tTC TA = 25°C, CL (of test probe) = 10 pF, CBYPASS = open – 45 – µs V VCC rising; UVLO is disabled, enabling the device Undervoltage Lockout (UVLO) UVLOD output – 3.8 4.2 V Threshold [1] V VCC falling; UVLO is enabled, disabling the device UVLOE output 3.45 3.7 – V UVLO Hysteresis VUVLO(HYS) TA = 25°C – 100 – mV t Time measured from falling VCC < VUVLOE to UVLO Enable/Disable UVLOE UVLO enabled – 74 – µs Delay Time t Time measured from rising VCC > VUVLOD to UVLOD UVLO disabled – 7 – µs Power-On Release Delay tPORD 3.3 V part variant only – 7 – µs V Power-On Reset Voltage PORH VCC rising – 2.8 – V VPORL VCC falling – 2.5 – V Power-On Reset Release Time tPORR TA = 25°C, VCC rising – 64 – µs Power-On Reset Hysteresis VHys(POR) – 250 – mV CL = 1 nF, device programmed to lowest bandwidth mode (default) – 140 – kHz Internal Bandwidth BWi CL = 1 nF, device programmed to highest bandwidth mode – 240 – kHz BW Rise Time [2] t TA = 25°C, CL = 1 nF, 1 V step on i = 240 kHz – 1.7 – µs r output, from 10% to 90% output BWi = 140 kHz – 3.2 – µs BW Propagation Delay Time [2] t TA = 25°C, CL = 1 nF, 1 V step on i = 240 kHz – 1 – µs PD output BWi = 140 kHz – 1.5 – µs BW Response Time [2] t TA = 25°C, CL = 1 nF, 1 V step on i = 240 kHz – 1.6 – µs RESPONSE output, 90% input to 90% output BWi = 140 kHz – 3.2 – µs DC Output Impedance ROUT – < 1 – Ω Output Load Resistance RLOAD(MIN) VOUT to GND 4.7 – – kΩ Output Load Capacitance CLOAD(MAX) VOUT to GND – 1 10 nF Output Voltage Clamp VCLP(HIGH) TA = 25°C, RL(PULLDWN) = 10 kΩ to GND 0.9 × VCC – – V (Clamp Enable Option Only) VCLP(LOW) TA = 25°C, RL(PULLUP) = 10 kΩ to VCC – – 0.1 × VCC V Delay to Clamp TA = 25°C; CL = 1nF; Step from 75% output range to (Clamp Enable Option Only) tCLP 150% – 5 – µs Output Saturation Voltage V (Clamp Disabled Option SAT(HIGH) TA = 25°C, RL(PULLDWN) = 10 kΩ to GND VCC – 0.2 – – V (Default) Only) VSAT(LOW) TA = 25°C, RL(PULLUP) = 10 kΩ to VCC – – 200 mV Continued on the next page… 5 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com