Datasheet PI6CB33602 (Diodes) - 4
| Fabricante | Diodes |
| Descripción | Very Low Power 6-Output PCIe Clock Buffer With On-Chip Termination |
| Páginas / Página | 20 / 4 — PI6CB33602. SMBus Address Selection Table. SADR. Address. +Read/Write … |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
PI6CB33602. SMBus Address Selection Table. SADR. Address. +Read/Write Bit. Power Management Table. PD#. SMBus OE bit. OEn#. Qn+. Qn-
Línea de modelo para esta hoja de datos
Versión de texto del documento
A product Line of Diodes Incorporated
PI6CB33602 SMBus Address Selection Table SADR Address +Read/Write Bit
0 1101011 X State of SADR on first application of PD# M 1101100 X 1 1101101 X
Power Management Table PD# IN SMBus OE bit OEn# Qn+ Qn- PLL Status
0 X X X Low(2) Low(2) Off 1 Running 0 X Low(2) Low(2) On(1) 1 Running 1 0 Running Running On(1) 1 Running 1 1 Low(2) Low(2) On(1)
Note:
1. If PLL Bypass mode is selected, the PLL will be off and outputs will be running. 2. The output state is set by B11[1:0] (Low/Low default)
PLL Operating Mode Select Table BW_SEL_TRI Operating Mode Byte1 [7:6] Readback Byte1 [4:3] Control
0 PLL with low Bandwidth 00 00 M PLL Bypass 01 01 1 PLL with high Bandwidth 11 11
Frequency Select table Freq. Select Byte 3 [4:3] IN (MHz) Qn (MHz)
00 (default) 100 100 01 50 50 10 125 125 11 133.33 133.33 PI6CB33602 www.diodes.com January 2020 Document Number DS41291 Rev 5-2 4 Diodes Incorporated
PI6CB33602 SMBus Address Selection Table SADR Address +Read/Write Bit
0 1101011 X State of SADR on first application of PD# M 1101100 X 1 1101101 X
Power Management Table PD# IN SMBus OE bit OEn# Qn+ Qn- PLL Status
0 X X X Low(2) Low(2) Off 1 Running 0 X Low(2) Low(2) On(1) 1 Running 1 0 Running Running On(1) 1 Running 1 1 Low(2) Low(2) On(1)
Note:
1. If PLL Bypass mode is selected, the PLL will be off and outputs will be running. 2. The output state is set by B11[1:0] (Low/Low default)
PLL Operating Mode Select Table BW_SEL_TRI Operating Mode Byte1 [7:6] Readback Byte1 [4:3] Control
0 PLL with low Bandwidth 00 00 M PLL Bypass 01 01 1 PLL with high Bandwidth 11 11
Frequency Select table Freq. Select Byte 3 [4:3] IN (MHz) Qn (MHz)
00 (default) 100 100 01 50 50 10 125 125 11 133.33 133.33 PI6CB33602 www.diodes.com January 2020 Document Number DS41291 Rev 5-2 4 Diodes Incorporated