Datasheet PI6CG33802C (Diodes) - 3

A product Line of Diodes Incorporated
PI6CG33802C Pin Description Cont. Pin # Pin Name Type Description
16 Q0- Output HCSL Differential complementary clock output 17 OE1# Input CMOS Active low input for enabling Q1 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 18 Q1+ Output HCSL Differential true clock output 19 Q1- Output HCSL Differential complementary clock output 20, 38 VDD Power — Power supply, nominal 3.3V 22, 40 GND Power — Ground 23 Q2+ Output HCSL Differential true clock output 24 Q2- Output HCSL Differential complementary clock output 25 OE2# Input CMOS Active low input for enabling Q2 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 26 Q3+ Output HCSL Differential true clock output 27 Q3- Output HCSL Differential complementary clock output 28 OE3# Input CMOS Active low input for enabling Q3 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 29 GNDA Power — Ground for analog circuitry 30 VDDA Power — Power supply for analog circuitry 32 Q4+ Output HCSL Differential true clock output 33 Q4- Output HCSL Differential complementary clock output 34 OE4# Input CMOS Active low input for enabling Q4 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 35 Q5+ Output HCSL Differential true clock output 36 Q5- Output HCSL Differential complementary clock output 37 OE5# Input CMOS Active low input for enabling Q5 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 41 Q6+ Output HCSL Differential true clock output 42 Q6- Output HCSL Differential complementary clock output 43 OE6# Input CMOS Active low input for enabling Q6 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 44 Q7+ Output HCSL Differential true clock output 45 Q7- Output HCSL Differential complementary clock output 46 OE7# Input CMOS Active low input for enabling Q7 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs Input notifies device to sample latched inputs and start up on first high 48 PD# Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. PI6CG33802C www.diodes.com January 2020 Document Number DS42298 Rev 3-2 3 Diodes Incorporated