Datasheet PI6CG33202C (Diodes)
| Fabricante | Diodes |
| Descripción | 3.3V Very Low Power 2-Output PCIe Clock Generator With On-chip Termination |
| Páginas / Página | 24 / 1 — Lead-free Green. PI6CG33202C. 3.3V Very Low Power 2-Output PCIe Clock … |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
Lead-free Green. PI6CG33202C. 3.3V Very Low Power 2-Output PCIe Clock Generator With On-chip Termination. Features. Description
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A product Line of
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Diodes Incorporated
Lead-free Green PI6CG33202C 3.3V Very Low Power 2-Output PCIe Clock Generator With On-chip Termination Features Description
Î Î 3.3V Supply Voltage The PI6CG33202C is a 2-output very low power PCIe Gen1/Gen2/ Î Î Crystal/CMOS input: 25 MHz Gen3/Gen4/Gen5 clock generator. It uses 25MHz crystal or CMOS Î Î 2 Differential low power HCSL outputs with on-chip termination reference as an input to generate the 100MHz low power dif- ferential HCSL outputs with on-chip terminations. The on-chip Î Î Default ZOUT = 85Ω termination can save 8 external resistors and make layout easier. Î Î Individual output enable An additional buffered reference output is provided to serve as a Î Î Reference CMOS output low noise reference for other circuitry. Î Î Programmable slew rate and output amplitude for each output It uses Diodes' proprietary PLL design to achieve very low Î Î Differential outputs blocked until PLL is locked jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 require- Î Î Selectable 0%, -0.25% or -0.5% spread on differential outputs ments. It also provides various options such as different slew rate Î Î Strapping pins or SMBus for configuration and amplitude through SMBUS so that users can configure the Î Î Differential Output-To-Output Skew <50ps device easily to get the optimized performance for their individ- Î Î Very-Low Jitter Outputs ual boards. The device also supports selectable spread-spectrum à Differential Cycle-To-Cycle Jitter <50ps options to reduce EMI for various applications. à PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Compliant à CMOS REFOUT Phase Jitter
Block Diagram
• < 0.3ps RMS, SSC off • <1.5ps RMS, SSC on REFOUT Î Î Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) OE[1:0]# Î Î Halogen and Antimony Free. “Green” Device (Note 3) Î Î For automotive applications requiring specific change control Q1 (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, XTAL_IN/CLK OSC PLL XTAL_OUT SS and manufactured in IATF 16949 certified facilities), please Q0 contact us or your local Diodes representative. SCLK https://www.diodes.com/quality/product-definitions/ SDATA SADR CTRL SS_SEL_TRI Î Î Packaging (Pb-free & Green): 24-lead 4×4mm TQFN LOGIC PD#
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. PI6CG33202C www.diodes.com January 2020 Document Number DS42292 Rev 3-2 1 Diodes Incorporated
b P
Diodes Incorporated
Lead-free Green PI6CG33202C 3.3V Very Low Power 2-Output PCIe Clock Generator With On-chip Termination Features Description
Î Î 3.3V Supply Voltage The PI6CG33202C is a 2-output very low power PCIe Gen1/Gen2/ Î Î Crystal/CMOS input: 25 MHz Gen3/Gen4/Gen5 clock generator. It uses 25MHz crystal or CMOS Î Î 2 Differential low power HCSL outputs with on-chip termination reference as an input to generate the 100MHz low power dif- ferential HCSL outputs with on-chip terminations. The on-chip Î Î Default ZOUT = 85Ω termination can save 8 external resistors and make layout easier. Î Î Individual output enable An additional buffered reference output is provided to serve as a Î Î Reference CMOS output low noise reference for other circuitry. Î Î Programmable slew rate and output amplitude for each output It uses Diodes' proprietary PLL design to achieve very low Î Î Differential outputs blocked until PLL is locked jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 require- Î Î Selectable 0%, -0.25% or -0.5% spread on differential outputs ments. It also provides various options such as different slew rate Î Î Strapping pins or SMBus for configuration and amplitude through SMBUS so that users can configure the Î Î Differential Output-To-Output Skew <50ps device easily to get the optimized performance for their individ- Î Î Very-Low Jitter Outputs ual boards. The device also supports selectable spread-spectrum à Differential Cycle-To-Cycle Jitter <50ps options to reduce EMI for various applications. à PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Compliant à CMOS REFOUT Phase Jitter
Block Diagram
• < 0.3ps RMS, SSC off • <1.5ps RMS, SSC on REFOUT Î Î Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) OE[1:0]# Î Î Halogen and Antimony Free. “Green” Device (Note 3) Î Î For automotive applications requiring specific change control Q1 (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, XTAL_IN/CLK OSC PLL XTAL_OUT SS and manufactured in IATF 16949 certified facilities), please Q0 contact us or your local Diodes representative. SCLK https://www.diodes.com/quality/product-definitions/ SDATA SADR CTRL SS_SEL_TRI Î Î Packaging (Pb-free & Green): 24-lead 4×4mm TQFN LOGIC PD#
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. PI6CG33202C www.diodes.com January 2020 Document Number DS42292 Rev 3-2 1 Diodes Incorporated