Datasheet PI6CG33201C (Diodes) - 8
| Fabricante | Diodes |
| Descripción | 3.3V Very Low Power 2-Output PCIe Clock Generator With On-chip Termination |
| Páginas / Página | 24 / 8 — PI6CG33201C. LVCMOS AC Characteristics. Symbol Parameters. Conditions. … |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
PI6CG33201C. LVCMOS AC Characteristics. Symbol Parameters. Conditions. Min. Typ. Max. Units. Note:
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A product Line of Diodes Incorporated
PI6CG33201C LVCMOS AC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
fINPUT Input Frequency XTAL_IN/CLK 25 MHz tRIN Input rise time Single-ended inputs 5 ns tFIN Input fall time Single-ended inputs 5 ns tSTAB Clock stabilization From Power-Up and after input clock stabi- lization or de-assertion of PD# to 1st clock 0.75 1 ms Q start after OE# assertion tOELAT Output enable latency 1 3 clocks Q stop after OE# deassertion tPDLAT PD# de-assertion Differential outputs enable after PD# de- assertion 20 300 us tPERIOD REFOUT clock period REFOUT, assume input is at 25MHz 40 ns fACC REFOUT frequency accuracy(1) REFOUT, long term accuracy to input 0 ppm Byte 3 = 1F, 20% to 80% of VDDREF 0.9 1.4 2 V/ns Byte 3 = 5F, 20% to 80% of V t DDREF 1.5 2.4 3.2 V/ns SLEW REFOUT slew rate(1) Byte 3 = 9F, 20% to 80% of VDDREF 2 3 3.8 V/ns Byte 3 = DF, 20% to 80% of VDDREF 2.3 3.2 4 V/ns tDC REFOUT Duty Cycle(1) VT = VDD /2 V, driven by a Xtal 45 50 55 % t REFOUT Duty Cycle Distor- VT = VDD /2 V, driven by an external DCDIS tion source -2 0 +2 % tJITCC REFOUT cycle-cycle jitter VT = VDD /2V, driven by a Xtal — 70 150 ps 12kHz to 5MHz, SSC off, driven by a Xtal — 0.16 0.3 ps tJITPH REFOUT Phase Jitter, RMS 12kHz to 5MHz, SSC on, driven by a Xtal — 0.9 1.5 ps 1kHz offset, driven by a Xtal — -149 -135 dBc/Hz tJITN Noise floor 10kHz offset to Nyquist, driven by a Xtal — -158 -140 dBc/Hz
Note:
1. Guaranteed by design and characterization, not 100% tested in production PI6CG33201C www.diodes.com January 2020 Document Number DS42291 Rev 3-2 8 Diodes Incorporated
PI6CG33201C LVCMOS AC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
fINPUT Input Frequency XTAL_IN/CLK 25 MHz tRIN Input rise time Single-ended inputs 5 ns tFIN Input fall time Single-ended inputs 5 ns tSTAB Clock stabilization From Power-Up and after input clock stabi- lization or de-assertion of PD# to 1st clock 0.75 1 ms Q start after OE# assertion tOELAT Output enable latency 1 3 clocks Q stop after OE# deassertion tPDLAT PD# de-assertion Differential outputs enable after PD# de- assertion 20 300 us tPERIOD REFOUT clock period REFOUT, assume input is at 25MHz 40 ns fACC REFOUT frequency accuracy(1) REFOUT, long term accuracy to input 0 ppm Byte 3 = 1F, 20% to 80% of VDDREF 0.9 1.4 2 V/ns Byte 3 = 5F, 20% to 80% of V t DDREF 1.5 2.4 3.2 V/ns SLEW REFOUT slew rate(1) Byte 3 = 9F, 20% to 80% of VDDREF 2 3 3.8 V/ns Byte 3 = DF, 20% to 80% of VDDREF 2.3 3.2 4 V/ns tDC REFOUT Duty Cycle(1) VT = VDD /2 V, driven by a Xtal 45 50 55 % t REFOUT Duty Cycle Distor- VT = VDD /2 V, driven by an external DCDIS tion source -2 0 +2 % tJITCC REFOUT cycle-cycle jitter VT = VDD /2V, driven by a Xtal — 70 150 ps 12kHz to 5MHz, SSC off, driven by a Xtal — 0.16 0.3 ps tJITPH REFOUT Phase Jitter, RMS 12kHz to 5MHz, SSC on, driven by a Xtal — 0.9 1.5 ps 1kHz offset, driven by a Xtal — -149 -135 dBc/Hz tJITN Noise floor 10kHz offset to Nyquist, driven by a Xtal — -158 -140 dBc/Hz
Note:
1. Guaranteed by design and characterization, not 100% tested in production PI6CG33201C www.diodes.com January 2020 Document Number DS42291 Rev 3-2 8 Diodes Incorporated