Datasheet AD73322 (Analog Devices) - 9

AD73322 (AVDD = +5 V
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10%; DVDD = +5 V
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10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
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C to +85
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C Units Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns typ SDI/SDIFS Setup Before SCLK Low t8 0 ns typ SDI/SDIFS Hold After SCLK Low t9 10 ns typ SDOFS Delay from SCLK High t10 10 ns typ SDOFS Hold After SCLK High t11 10 ns typ SDO Hold After SCLK High t12 10 ns typ SDO Delay from SCLK High t13 30 ns typ SCLK Delay from MCLK Specifications subject to change without notice.
t1 100
m
A IOL t2 TO OUTPUT +2.1V PIN CL 15pF 100
m
A I t OH 3
Figure 1. MCLK Timing Figure 2. Load Circuit for Timing Specifications
t t2 t 1 3 MCLK t13 t t SCLK* 5 6 t4 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I) THREE- STATE SCLK (O) t7 SDIFS (I) t8 t8 t7 SDI (I) D15 D14 D1 D0 D15 THREE- t t 9 10 STATE SDOFS (O) t t THREE- 12 11 STATE SDO (O) D15 D2 D1 D0 D15 D14
Figure 4. Serial Port (SPORT) REV. B –9–