Datasheet AD73322 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| Páginas / Página | 43 / 5 — AD73322. SPECIFICATIONS1 (AVDD = +5 V. 10%; DVDD = +5 V. 10%; DGND = AGND … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 396 Kb |
| Idioma del documento | Inglés |
AD73322. SPECIFICATIONS1 (AVDD = +5 V. 10%; DVDD = +5 V. 10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz;
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AD73322 SPECIFICATIONS1 (AVDD = +5 V
ⴞ
10%; DVDD = +5 V
ⴞ
10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted) AD73322A Parameter Min Typ Max Units Test Conditions/Comments
REFERENCE REFCAP Absolute Voltage, VREFCAP 1.2 V 5VEN = 0 2.4 V 5VEN = 1 REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFOUT REFCAP to AGND2 Typical Output Impedance 130 Ω Absolute Voltage, VREFOUT 1.2 V 5VEN = 0, Unloaded 2.4 V 5VEN = 1, Unloaded Minimum Load Resistance 2 kΩ 5VEN = 1 Maximum Load Capacitance 100 pF INPUT AMPLIFIER Offset ±1.0 mV Maximum Output Swing 3.156 V Max Output Swing = (3.156/2.4) × VREFCAP Feedback Resistance 50 kΩ fC = 32 kHz Feedback Capacitance 100 pF ANALOG GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 5 Bits Gain Step Size = 0.0625 Gain Accuracy ±1 % Output Unloaded Settling Time 1.0 µs Tap Gain Change of –FS to +FS Delay 0.5 µs ADC SPECIFICATIONS 5VEN = 1 Maximum Input Range at VIN2, 3 3.156 V p-p Measured Differentially 3.17 dBm Max Input Swing = (3.156/2.4) × VREFCAP Nominal Reference Level at VIN 2.1908 V p-p Measured Differentially (0 dBm0) 0 dBm Absolute Gain PGA = 0 dB 0.4 dB 1.0 kHz, 0 dBm0 PGA = 38 dB –0.7 dB 1.0 kHz, 0 dBm0 Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0 Signal to (Noise + Distortion) Refer to Figure 7 PGA = 0 dB 78 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz 78 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz 57 dB 0 Hz to fSAMP/2; fSAMP = 64 kHz PGA = 38 dB 56 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Total Harmonic Distortion PGA = 0 dB –84 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz PGA = 38 dB –70 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Intermodulation Distortion –65 dB PGA = 0 dB Idle Channel Noise –71 dBm0 PGA = 0 dB Crosstalk ADC-to-DAC –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle ADC-to-ADC –100 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle. Input Amplifiers Bypassed –70 dB Input Amplifiers Included in Channel DC Offset +10 mV PGA = 0 dB Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave Group Delay4, 5 25 µs 64 kHz Output Sample Rate Input Resistance at PGA2, 4, 6 20 kΩ Input Amplifiers Bypassed REV. B –5–
ⴞ
10%; DVDD = +5 V
ⴞ
10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted) AD73322A Parameter Min Typ Max Units Test Conditions/Comments
REFERENCE REFCAP Absolute Voltage, VREFCAP 1.2 V 5VEN = 0 2.4 V 5VEN = 1 REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFOUT REFCAP to AGND2 Typical Output Impedance 130 Ω Absolute Voltage, VREFOUT 1.2 V 5VEN = 0, Unloaded 2.4 V 5VEN = 1, Unloaded Minimum Load Resistance 2 kΩ 5VEN = 1 Maximum Load Capacitance 100 pF INPUT AMPLIFIER Offset ±1.0 mV Maximum Output Swing 3.156 V Max Output Swing = (3.156/2.4) × VREFCAP Feedback Resistance 50 kΩ fC = 32 kHz Feedback Capacitance 100 pF ANALOG GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 5 Bits Gain Step Size = 0.0625 Gain Accuracy ±1 % Output Unloaded Settling Time 1.0 µs Tap Gain Change of –FS to +FS Delay 0.5 µs ADC SPECIFICATIONS 5VEN = 1 Maximum Input Range at VIN2, 3 3.156 V p-p Measured Differentially 3.17 dBm Max Input Swing = (3.156/2.4) × VREFCAP Nominal Reference Level at VIN 2.1908 V p-p Measured Differentially (0 dBm0) 0 dBm Absolute Gain PGA = 0 dB 0.4 dB 1.0 kHz, 0 dBm0 PGA = 38 dB –0.7 dB 1.0 kHz, 0 dBm0 Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0 Signal to (Noise + Distortion) Refer to Figure 7 PGA = 0 dB 78 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz 78 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz 57 dB 0 Hz to fSAMP/2; fSAMP = 64 kHz PGA = 38 dB 56 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Total Harmonic Distortion PGA = 0 dB –84 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz PGA = 38 dB –70 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz Intermodulation Distortion –65 dB PGA = 0 dB Idle Channel Noise –71 dBm0 PGA = 0 dB Crosstalk ADC-to-DAC –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle ADC-to-ADC –100 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle. Input Amplifiers Bypassed –70 dB Input Amplifiers Included in Channel DC Offset +10 mV PGA = 0 dB Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave Group Delay4, 5 25 µs 64 kHz Output Sample Rate Input Resistance at PGA2, 4, 6 20 kΩ Input Amplifiers Bypassed REV. B –5–