Datasheet AD73311L (Analog Devices) - 9

AD73311L FUNCTIONAL DESCRIPTION
sampling rate of the sigma-delta modulator is DMCLK/8. The
Encoder Channel
main effect of oversampling is that the quantization noise is The encoder channel consists of an input configuration block, a spread over a very wide bandwidth, up to FS/2 = DMCLK/16 switched capacitor PGA and a sigma-delta analog-to-digital (Figure 6a). This means that the noise in the band of interest is converter (ADC). An on-board digital filter, which forms part much reduced. Another complementary feature of sigma-delta of the sigma-delta ADC, also performs critical system-level converters is the use of a technique called noise-shaping. This filtering. Due to the high level of oversampling, the input anti- technique has the effect of pushing the noise from the band of alias requirements are reduced such that a simple single pole interest to an out-of-band position (Figure 6b). The combi- RC stage is sufficient to give adequate attenuation in the band nation of these techniques, followed by the application of a of interest. digital filter, reduces the noise in band sufficiently to ensure good dynamic performance from the part (Figure 6c).
Input Configuration Block
The input configuration block consists of a multiplexing arrange- ment that allows selection of various input configurations. This includes ADC input selection from either the VINP, VINN pins or from the DAC output via the Analog Loop-Back (ALB) arrangement. Differential inputs can be inverted and it is also possible to use the device in single-ended mode, which allows the option of using the VINP, VINN pins as two separate
BAND F OF S/2
single-ended inputs, either of which can be selected under
INTEREST DMCLK/16
software control. a.
Programmable Gain Amplifier
The encoder section’s analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table III, may be
NOISE-SHAPING
used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid
BAND F OF S/2
placing external amplifiers in the circuit. The input signal level
INTEREST DMCLK/16
to the sigma-delta modulator should not exceed the maximum b. input voltage permitted. The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2) in Control Register D.
DIGITAL FILTER Table III. PGA Settings for the Encoder Channel IGS2 IGS1 IGS0 Gain (dB) BAND FS/2
0 0 0 0
OF INTEREST DMCLK/16
0 0 1 6 c. 0 1 0 12 Figure 6. Sigma-Delta Noise Reduction 0 1 1 18 1 0 0 20 Figure 7 shows the various stages of filtering that are employed 1 0 1 26 in a typical AD73311L application. In Figure 7a we see the 1 1 0 32 transfer function of the external analog antialias filter. Even 1 1 1 38 though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling
ADC
frequency. This also shows the major difference between the The ADC consists of an analog sigma-delta modulator and a initial oversampling rate and the bandwidth of interest. In Figure digital antialiasing decimation filter. The sigma-delta modu- 7b, the signal and noise-shaping responses of the sigma-delta lator noise-shapes the signal and produces 1-bit samples at a modulator are shown. The signal response provides further DMCLK/8 rate. This bitstream, representing the analog input rejection of any high frequency signals while the noise-shaping signal, is input to the antialiasing decimation filter. The decima- will push the inherent quantization noise to an out-of-band tion filter reduces the sample rate and increases the resolution. position. The detail of Figure 7c shows the response of the
Analog Sigma-Delta Modulator
digital decimation filter (Sinc-cubed response) with nulls every The AD73311L input channel employs a sigma-delta conver- multiple of DMCLK/256, which is the decimation filter update sion technique, which provides a high resolution 16-bit output rate. The final detail in Figure 7d shows the application of a with system filtering being implemented on-chip. final antialias filter in the DSP engine. This has the advantage Sigma-delta converters employ a technique known as over- of being implemented according to the user’s requirements and sampling, where the sampling rate is many times the highest available MIPS. The filtering in Figures 7a through 7c is imple- frequency of interest. In the case of the AD73311L, the initial mented in the AD73311L. REV. A –9–