Datasheet AD74111 (Analog Devices) - 9

AD74111 ADC 8 f 4 f 2 f f 5th ORDER S S COMB S S ADC MODULATOR HALF-BAND COMB FILTER HALF-BAND COMPENSATION RESULT 64 fS LOW GROUP DELAY OUTPUT
Figure 5a. ADC Filter Section
DAC 8 f 4 f 2 f f S S ZERO ORDER HOLD S S DAC MODULATOR 16 ZERO HALF-BAND HALF-BAND– SINC COMPENSATION INPUT 128 f ORDER HOLD FILTER FILTER S FILTER LOW GROUP DELAY INPUT
Figure 5b. DAC Filter Section
ADC, CAPP, and CAPN Pins Output Signal Swing
The ADC channel requires two external capacitors to act as The DAC has an output range of 0.5 V rms/1.414 V p-p about charge reservoirs for the switched capacitor inputs of the sigma- a bias point equal to VREFCAP (see Figure 7). delta modulator. These capacitors isolate the outputs of the PGA stage from glitches generated by the sigma-delta modulator. The capacitor also forms a low-pass filter with the output impedance
VREFCAP VOUT 1.414V p-p
of the PGA (approximately 124 Ω), which helps to isolate noise
820 2n2F
from the modulator engine. The capacitors should be of good
NPO
quality, such as NPO or polypropylene film, with values from 100 pF to 1 nF and should be connected to AGND. Figure 7. Typical Output Circuit
Peak Readback
The AD74111 can store the highest ADC value to facilitate level
Low Group Delay
adjustment of the input signal. Programming the Peak Enable It is possible to bypass much of the digital filtering by enabling bit in Control Register E with a 1 will enable ADC Peak Level the Low Group Delay function in Control Register C. By reduc- Reading. The peak value is stored as a 6-bit number from 0 dB ing the amount of filtering the AD74111 applies to input and to –63 dB in 1 dB steps. Reading Control Register F will give the output samples, the time delay between the sampling interval highest ADC value since the bit was set. The ADC peak register and when the sample is available is greatly reduced. This can be is automatically cleared after reading. of benefit in applications such as telematics, where minimal time delays are important. When the Low Group Delay function
Decimator Section
is enabled, the sample rate becomes IMCLK/128. The digital decimation filter has a pass-band ripple of 0.2 mdB and a stop-band attenuation of 120 dB. The filter is an FIR type
Reference
with a linear phase response. The group delay at 48 kHz is The AD74111 features an on-chip reference whose nominal 910 µs. Output sample rates up to 48 kHz are supported. value is 1.125 V. A 100 nF ceramic and 10 µF tantalum capacitor applied at the REFCAP pin are necessary to stabilize the reference.
Input Signal Swing
(See Figure 8.) The ADC input has an input range of 0.5 V rms/1.414 V p-p about a bias point equal to VREFCAP. Figure 6 shows a typical input filter circuit for use with the AD74111.
REFCAP 10 F 0.1 F V AGND 51 1.414V p-p VIN 10nF 47 F NPO
Figure 8. Reference Decoupling If required, an external reference can be used as the reference Figure 6. Typical Input Circuit source of the ADC and DAC sections. This may be desirable in situations where multiple devices are required to use the same
DAC Section
value of reference or because of a better temperature coefficient The AD74111 DAC channel has a single-ended, analog output. specification. The internal reference can be disabled via Control The DAC has independent software controllable Mute and Volume Register A and the external reference applied at the REFCAP Control functions. Control Register G controls the attenuation pin (see Figure 9). External references should be of a suitable factor for the DAC. This register is 10 bits wide, giving 1024 value such that the voltage swing of the inputs or outputs is not steps of attenuation. The AD74111 output channel employs a affected by being too close to the power supply rails and should multibit sigma-delta conversion technique that provides a high be adequately decoupled. quality output with system filtering implemented on-chip. REV. 0 –9– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics FUNCTIONAL DESCRIPTION General Description ADC Section ADC, CAPP, and CAPN Pins Peak Readback Decimator Section Input Signal Swing DAC Section Output Signal Swing Low Group Delay Reference Master Clocking Scheme Selecting Sample Rates Resetting the AD74111 Power Supplies and Grounds Accessing the Internal Registers Serial Port Serial Port Operating Modes Mixed Mode Data Mode Data-Word Length Selecting Master or Slave Mode Master Mode Operation Slave Mode Operation OUTLINE DIMENSIONS