Datasheet AD1938 (Analog Devices) - 7

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Data Sheet AD1938 TIMING SPECIFICATIONS
−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.
Table 7. Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 40 60 % 384 fS, 512 fS, and 768 fS tMH DAC/ADC clock source = direct MCLK @ 512 fS 40 60 % (bypass on-chip PLL) fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR RST low 15 ns tPDRR RST recovery Reset to active output 4096 tMCLK PLL Lock time MCLK and LR clock input 10 ms 256 fS VCO Clock, Output Duty Cycle, 40 60 % MCLKO/XO Pin SPI PORT See Figure 11 tCCH CCLK high 35 ns tCCL CCLK low 35 ns fCCLK CCLK frequency fCCLK = 1/tCCP, only tCCP shown in Figure 11 10 MHz tCDS CIN setup To CCLK rising 10 ns tCDH CIN hold From CCLK rising 10 ns tCLS CLATCH setup To CCLK rising 10 ns tCLH CLATCH hold From CCLK rising 10 ns tCLH CLATCH high Not shown in Figure 11 10 ns tCOE COUT enable From CCLK falling 30 ns tCOD COUT delay From CCLK falling 30 ns tCOH COUT hold From CCLK falling, not shown in Figure 11 30 ns tCOTS COUT tristate From CCLK falling 30 ns DAC SERIAL PORT See Figure 24 tDBH DBCLK high Slave mode 10 ns tDBL DBCLK low Slave mode 10 ns tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To DBCLK rising 10 ns tDDH DSDATA hold From DBCLK rising 5 ns ADC SERIAL PORT See Figure 25 tABH ABCLK high Slave mode 10 ns tABL ABCLK low Slave mode 10 ns tALS ALRCLK setup To ABCLK rising, slave mode 10 ns tALH ALRCLK hold From ABCLK rising, slave mode 5 ns tALS ALRCLK skew From ABCLK falling, master mode −8 +8 ns tABDD ASDATA delay From ABCLK falling 18 ns AUXILIARY INTERFACE tAXDS AAUXDATA setup To AUXBCLK rising 10 ns tAXDH AAUXDATA hold From AUXBCLK rising 5 ns tDXDD DAUXDATA delay From AUXBCLK falling 18 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tDLS AUXLRCLK setup To AUXBCLK rising 10 ns tDLH AUXLRCLK hold From AUXBCLK rising 5 ns Rev. E | Page 7 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Applications Circuits Outline Dimensions Ordering Guide Automotive Products