Datasheet ADAU1361 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| Páginas / Página | 80 / 2 — ADAU1361. Data Sheet. TABLE OF CONTENTS |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
ADAU1361. Data Sheet. TABLE OF CONTENTS
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 1 link to page 1 link to page 1 link to page 1 link to page 3 link to page 4 link to page 4 link to page 7 link to page 8 link to page 9 link to page 10 link to page 10 link to page 11 link to page 12 link to page 14 link to page 14 link to page 14 link to page 15 link to page 17 link to page 20 link to page 23 link to page 24 link to page 24 link to page 24 link to page 24 link to page 24 link to page 24 link to page 26 link to page 26 link to page 26 link to page 27 link to page 29 link to page 29 link to page 31 link to page 32 link to page 32 link to page 33 link to page 35 link to page 35 link to page 36 link to page 37 link to page 37 link to page 38 link to page 38 link to page 38 link to page 41 link to page 42 link to page 44 link to page 44 link to page 44 link to page 44 link to page 44 link to page 45 link to page 46 link to page 79 link to page 79
ADAU1361 Data Sheet TABLE OF CONTENTS
Features .. 1 Core Clock ... 26 Applications ... 1 Sampling Rates .. 26 General Description ... 1 PLL ... 27 Functional Block Diagram .. 1 Record Signal Path ... 29 Revision History ... 3 Input Signal Paths ... 29 Specifications ... 4 Analog-to-Digital Converters ... 31 Analog Performance Specifications ... 4 Automatic Level Control (ALC) ... 32 Power Supply Specifications.. 7 ALC Parameters .. 32 Typical Current Consumption .. 8 Noise Gate Function .. 33 Typical Power Management Measurements ... 9 Playback Signal Path .. 35 Digital Filters ... 10 Output Signal Paths ... 35 Digital Input/Output Specifications... 10 Headphone Output .. 36 Digital Timing Specifications ... 11 Pop-and-Click Suppression .. 37 Digital Timing Diagrams... 12 Line Outputs ... 37 Absolute Maximum Ratings .. 14 Control Ports ... 38 Thermal Resistance .. 14 Burst Mode Writing and Reading .. 38 ESD Caution .. 14 I2C Port .. 38 Pin Configuration and Function Descriptions ... 15 SPI Port .. 41 Typical Performance Characteristics ... 17 Serial Data Input/Output Ports .. 42 System Block Diagrams ... 20 Applications Information .. 44 Theory of Operation .. 23 Power Supply Bypass Capacitors .. 44 Startup, Initialization, and Power ... 24 GSM Noise Filter .. 44 Power-Up Sequence ... 24 Grounding ... 44 Power Reduction Modes .. 24 Exposed Pad PCB Design ... 44 Digital Power Supply .. 24 Control Registers .. 45 Input/Output Power Supply .. 24 Control Register Details .. 46 Clock Generation and Management .. 24 Outline Dimensions ... 79 Clocking and Sampling Rates ... 26 Ordering Guide .. 79 Rev. D | Page 2 of 80 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Power Supply Specifications Typical Current Consumption Typical Power Management Measurements Digital Filters Digital Input/Output Specifications Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation Startup, Initialization, and Power Power-Up Sequence Power Reduction Modes Digital Power Supply Input/Output Power Supply Clock Generation and Management Case 1: PLL Is Bypassed Case 2: PLL Is Used PLL Lock Acquisition Clocking and Sampling Rates Core Clock Sampling Rates PLL Integer Mode Fractional Mode Record Signal Path Input Signal Paths Analog Microphone Inputs Analog Line Inputs Digital Microphone Input Microphone Bias Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Automatic Level Control (ALC) ALC Parameters Noise Gate Function Playback Signal Path Output Signal Paths Routing Flexibility Headphone Output Capless Headphone Configuration Headphone Output Power-Up/Power-Down Sequencing Ground-Centered Headphone Configuration Jack Detection Pop-and-Click Suppression Line Outputs Control Ports Burst Mode Writing and Reading I2C Port Addressing I2C Read and Write Operations SPI Port Chip Address R/ Subaddress Data Bytes Serial Data Input/Output Ports Applications Information Power Supply Bypass Capacitors GSM Noise Filter Grounding Exposed Pad PCB Design Control Registers Control Register Details R0: Clock Control, 16,384 (0x4000) R1: PLL Control, 16,386 (0x4002) R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) R3: Record Power Management, 16,393 (0x4009) R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) R8: Left Differential Input Volume Control, 16,398 (0x400E) R9: Right Differential Input Volume Control, 16,399 (0x400F) R10: Record Microphone Bias Control, 16,400 (0x4010) R11: ALC Control 0, 16,401 (0x4011) R12: ALC Control 1, 16,402 (0x4012) R13: ALC Control 2, 16,403 (0x4013) R14: ALC Control 3, 16,404 (0x4014) R15: Serial Port Control 0, 16,405 (0x4015) R16: Serial Port Control 1, 16,406 (0x4016) R17: Converter Control 0, 16,407 (0x4017) R18: Converter Control 1, 16,408 (0x4018) R19: ADC Control, 16,409 (0x4019) R20: Left Input Digital Volume, 16,410 (0x401A) R21: Right Input Digital Volume, 16,411 (0x401B) R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C) R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) R29: Playback Headphone Left Volume Control, 16,419 (0x4023) R30: Playback Headphone Right Volume Control, 16,420 (0x4024) R31: Playback Line Output Left Volume Control, 16,421 (0x4025) R32: Playback Line Output Right Volume Control, 16,422 (0x4026) R33: Playback Mono Output Control, 16,423 (0x4027) R34: Playback Pop/Click Suppression, 16,424 (0x4028) R35: Playback Power Management, 16,425 (0x4029) R36: DAC Control 0, 16,426 (0x402A) R37: DAC Control 1, 16,427 (0x402B) R38: DAC Control 2, 16,428 (0x402C) R39: Serial Port Pad Control, 16,429 (0x402D) R40: Control Port Pad Control 0, 16,431 (0x402F) R41: Control Port Pad Control 1, 16,432 (0x4030) R42: Jack Detect Pin Control, 16,433 (0x4031) R67: Dejitter Control, 16,438 (0x4036) Outline Dimensions Ordering Guide
ADAU1361 Data Sheet TABLE OF CONTENTS
Features .. 1 Core Clock ... 26 Applications ... 1 Sampling Rates .. 26 General Description ... 1 PLL ... 27 Functional Block Diagram .. 1 Record Signal Path ... 29 Revision History ... 3 Input Signal Paths ... 29 Specifications ... 4 Analog-to-Digital Converters ... 31 Analog Performance Specifications ... 4 Automatic Level Control (ALC) ... 32 Power Supply Specifications.. 7 ALC Parameters .. 32 Typical Current Consumption .. 8 Noise Gate Function .. 33 Typical Power Management Measurements ... 9 Playback Signal Path .. 35 Digital Filters ... 10 Output Signal Paths ... 35 Digital Input/Output Specifications... 10 Headphone Output .. 36 Digital Timing Specifications ... 11 Pop-and-Click Suppression .. 37 Digital Timing Diagrams... 12 Line Outputs ... 37 Absolute Maximum Ratings .. 14 Control Ports ... 38 Thermal Resistance .. 14 Burst Mode Writing and Reading .. 38 ESD Caution .. 14 I2C Port .. 38 Pin Configuration and Function Descriptions ... 15 SPI Port .. 41 Typical Performance Characteristics ... 17 Serial Data Input/Output Ports .. 42 System Block Diagrams ... 20 Applications Information .. 44 Theory of Operation .. 23 Power Supply Bypass Capacitors .. 44 Startup, Initialization, and Power ... 24 GSM Noise Filter .. 44 Power-Up Sequence ... 24 Grounding ... 44 Power Reduction Modes .. 24 Exposed Pad PCB Design ... 44 Digital Power Supply .. 24 Control Registers .. 45 Input/Output Power Supply .. 24 Control Register Details .. 46 Clock Generation and Management .. 24 Outline Dimensions ... 79 Clocking and Sampling Rates ... 26 Ordering Guide .. 79 Rev. D | Page 2 of 80 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Power Supply Specifications Typical Current Consumption Typical Power Management Measurements Digital Filters Digital Input/Output Specifications Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation Startup, Initialization, and Power Power-Up Sequence Power Reduction Modes Digital Power Supply Input/Output Power Supply Clock Generation and Management Case 1: PLL Is Bypassed Case 2: PLL Is Used PLL Lock Acquisition Clocking and Sampling Rates Core Clock Sampling Rates PLL Integer Mode Fractional Mode Record Signal Path Input Signal Paths Analog Microphone Inputs Analog Line Inputs Digital Microphone Input Microphone Bias Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Automatic Level Control (ALC) ALC Parameters Noise Gate Function Playback Signal Path Output Signal Paths Routing Flexibility Headphone Output Capless Headphone Configuration Headphone Output Power-Up/Power-Down Sequencing Ground-Centered Headphone Configuration Jack Detection Pop-and-Click Suppression Line Outputs Control Ports Burst Mode Writing and Reading I2C Port Addressing I2C Read and Write Operations SPI Port Chip Address R/ Subaddress Data Bytes Serial Data Input/Output Ports Applications Information Power Supply Bypass Capacitors GSM Noise Filter Grounding Exposed Pad PCB Design Control Registers Control Register Details R0: Clock Control, 16,384 (0x4000) R1: PLL Control, 16,386 (0x4002) R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) R3: Record Power Management, 16,393 (0x4009) R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) R8: Left Differential Input Volume Control, 16,398 (0x400E) R9: Right Differential Input Volume Control, 16,399 (0x400F) R10: Record Microphone Bias Control, 16,400 (0x4010) R11: ALC Control 0, 16,401 (0x4011) R12: ALC Control 1, 16,402 (0x4012) R13: ALC Control 2, 16,403 (0x4013) R14: ALC Control 3, 16,404 (0x4014) R15: Serial Port Control 0, 16,405 (0x4015) R16: Serial Port Control 1, 16,406 (0x4016) R17: Converter Control 0, 16,407 (0x4017) R18: Converter Control 1, 16,408 (0x4018) R19: ADC Control, 16,409 (0x4019) R20: Left Input Digital Volume, 16,410 (0x401A) R21: Right Input Digital Volume, 16,411 (0x401B) R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C) R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) R29: Playback Headphone Left Volume Control, 16,419 (0x4023) R30: Playback Headphone Right Volume Control, 16,420 (0x4024) R31: Playback Line Output Left Volume Control, 16,421 (0x4025) R32: Playback Line Output Right Volume Control, 16,422 (0x4026) R33: Playback Mono Output Control, 16,423 (0x4027) R34: Playback Pop/Click Suppression, 16,424 (0x4028) R35: Playback Power Management, 16,425 (0x4029) R36: DAC Control 0, 16,426 (0x402A) R37: DAC Control 1, 16,427 (0x402B) R38: DAC Control 2, 16,428 (0x402C) R39: Serial Port Pad Control, 16,429 (0x402D) R40: Control Port Pad Control 0, 16,431 (0x402F) R41: Control Port Pad Control 1, 16,432 (0x4030) R42: Jack Detect Pin Control, 16,433 (0x4031) R67: Dejitter Control, 16,438 (0x4036) Outline Dimensions Ordering Guide