Datasheet ADAU1372 (Analog Devices) - 10

link to page 12
ADAU1372 Data Sheet DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing Parameter tMIN tMAX Unit Description
MASTER CLOCK tMP 37 125 ns MCLKIN period; 8 MHz to 27 MHz input clock using PLL tMCLK 77 82 ns Internal MCLK period; direct MCLK and PLL output divided by 2 SERIAL PORT tBL 40 ns BCLK low pulse width (master and slave modes) tBH 40 ns BCLK high pulse width (master and slave modes) tLS 10 ns LRCLK setup; time to BCLK rising (slave mode) tLH 10 ns LRCLK hold; time from BCLK rising (slave mode) tSS 5 ns DAC_SDATA setup; time to BCLK rising (master and slave modes) tSH 5 ns DAC_SDATA hold; time from BCLK rising (master and slave modes) tTS 10 ns BCLK falling to LRCLK timing skew (master mode) tSOD 0 34 ns ADC_SDATAx delay; time from BCLK fal ing (master and slave modes) tSOTD 30 ns BCLK fal ing to ADC_SDATAx driven in time-division multiplexing (TDM) tristate mode tSOTX 30 ns BCLK fal ing to ADC_SDATAx tristate in TDM tristate mode SPI PORT fSCLK 6.25 MHz SCLK frequency tCCPL 80 ns SCLK pulse width low tCCPH 80 ns SCLK pulse width high tCLS 5 ns SS setup; time to SCLK rising tCLH 100 ns SS hold; time from SCLK rising tCLPH 80 ns SS pulse width high tCDS 10 ns MOSI setup; time to SCLK rising tCDH 10 ns MOSI hold; time from SCLK rising tCOD 101 ns MISO delay; time from SCLK falling I2C PORT fSCL 400 kHz SCL frequency tSCLH 0.6 µs SCL high tSCLL 1.3 µs SCL low tSCS 0.6 µs SCL rise setup time (to SDA fal ing), relevant for repeated start condition tSCR 250 ns SCL and SDA rise time, CLOAD = 400 pF tSCH 0.6 µs SCL fall hold time (from SDA falling), relevant for start condition tDS 100 ns SDA setup time (to SCL rising) tSCF 250 ns SCL fall time; CLOAD = 400 pF tSDF 250 ns SDA fall time; CLOAD = 400 pF; not shown in Figure 5 tBFT 0.6 µs SCL rise setup time (to SDA rising), relevant for stop condition MULTIPURPOSE AND POWER- DOWN PINS tGIL 1.5 × 1/fS µs MPx input latency; time until high or low value is read tRLPW 20 ns PD low pulse width DIGITAL MICROPHONE tCF 20 ns Digital microphone clock fall time tCR 20 ns Digital microphone clock rise time tDS 40 Digital microphone valid data start time tDE 0 ns Digital microphone valid data end time Rev. 0 | Page 10 of 92 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT/OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP INITIALIZATION CLOCK INITIALIZATION PLL Bypass Setup PLL Enabled Setup Control Port Access During Initialization PLL Input Clock Divider Integer Mode Fractional Mode CLOCK OUTPUT POWER SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Signal Polarity Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias DIGITAL MICROPHONE INPUT ANALOG-TO-DIGITAL CONVERTERS ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Headphone Output Power-Up Sequencing Ground Centered Headphone Configuration Pop and Click Suppression Line Outputs DIGITAL-TO-ANALOG CONVERTERS DAC Full-Scale Level Digital DAC Volume Control ASYNCHRONOUS SAMPLE RATE CONVERTERS CONTROL PORT BURST MODE COMMUNICATION I2C PORT Addressing I2C Read and Write Operations SPI PORT Read/Write Subaddress Data Bytes BURST MODE COMMUNICATION MULTIPURPOSE PINS PUSH-BUTTON VOLUME CONTROLS MUTE TALKTHROUGH MODE SERIAL DATA INPUT/OUTPUT PORTS SERIAL PORT INITIALIZATION TRISTATING UNUSED CHANNELS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING EXPOSED PAD PCB DESIGN SYSTEM BLOCK DIAGRAM REGISTER SUMMARY: LOW LATENCY CODEC CLOCK CONTROL REGISTER PLL DENOMINATOR MSB REGISTER PLL DENOMINATOR LSB REGISTER PLL NUMERATOR MSB REGISTER PLL NUMERATOR LSB REGISTER PLL INTEGER SETTING REGISTER PLL LOCK FLAG REGISTER CLKOUT SETTING SELECTION REGISTER REGULATOR CONTROL REGISTER DAC INPUT SELECT REGISTER SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER SERIAL DATA OUTPUT 6/SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER ADC_SDATA0/ADC_SDATA1 CHANNEL SELECT REGISTER OUTPUT ASRC0/OUTPUT ASRC1 SOURCE REGISTER OUTPUT ASRC2/OUTPUT ASRC3 SOURCE REGISTER INPUT ASRC CHANNEL SELECT REGISTER ADC CONTROL 0 REGISTER ADC CONTROL 1 REGISTER ADC CONTROL 2 REGISTER ADC CONTROL 3 REGISTER ADC0 VOLUME CONTROL REGISTER ADC1 VOLUME CONTROL REGISTER ADC2 VOLUME CONTROL REGISTER ADC3 VOLUME CONTROL REGISTER PGA CONTROL 0 REGISTER PGA CONTROL 1 REGISTER PGA CONTROL 2 REGISTER PGA CONTROL 3 REGISTER PGA SLEW CONTROL REGISTER PGA 10 dB GAIN BOOST REGISTER INPUT AND OUTPUT CAPACITOR CHARGING REGISTER ADC TO DAC TALKTHROUGH BYPASS PATH REGISTER TALKTHROUGH BYPASS GAIN FOR ADC0 REGISTER TALKTHROUGH BYPASS GAIN FOR ADC1 REGISTER MICBIAS CONTROL REGISTER DAC CONTROL 1 REGISTER DAC0 VOLUME CONTROL REGISTER DAC1 VOLUME CONTROL REGISTER HEADPHONE OUTPUT MUTES REGISTER SERIAL PORT CONTROL 0 REGISTER SERIAL PORT CONTROL 1 REGISTER TDM OUTPUT CHANNEL DISABLE REGISTER MP0 FUNCTION SETTING REGISTER MP1 FUNCTION SETTING REGISTER MP4 FUNCTION SETTING REGISTER MP5 FUNCTION SETTING REGISTER MP6 FUNCTION SETTING REGISTER PUSH-BUTTON VOLUME SETTINGS REGISTER PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER DEBOUNCE MODES REGISTER HEADPHONE LINE OUTPUT SELECT REGISTER DECIMATOR POWER CONTROL REGISTER ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER ANALOG BIAS CONTROL 0 REGISTER ANALOG BIAS CONTROL 1 REGISTER DIGITAL PIN PULL-UP CONTROL 0 REGISTER DIGITAL PIN PULL-UP CONTROL 1 REGISTER DIGITAL PIN PULL-DOWN CONTROL 2 REGISTER DIGITAL PIN PULL-DOWN CONTROL 3 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 4 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 5 REGISTER OUTLINE DIMENSIONS ORDERING GUIDE