Datasheet STSPIN32F0251, STSPIN32F0252 (STMicroelectronics) - 6

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Pin description and connection diagram STSPIN32F0251, STSPIN32F0252 Table 2. Pin description (continued) N. Name Type Function
14 PA2 I/O - TTa MCU PA2 15 PA3 I/O - TTa MCU PA3 16 PA4 I/O - TTa MCU PA4 17 PA5 I/O - TTa MCU PA5 18 PA6 I/O - TTa MCU PA6 19 PA7 I/O - TTa MCU PA7 20 PB0 I/O - TTa MCU PB0 21 PB1 I/O - TTa MCU PB1 22 VDD Supply MCU digital power supply 23 VSS Supply MCU digital ground 24 OD Analog OD Output Open Drain comparator output 25 CIN Analog Input Comparator positive input 26 SGND Power Driver signal ground 27 PGND Power Driver power ground 28 LVG1(1) Analog Out Phase 1 low-side driver output 29 LVG2 Analog Out Phase 2 low-side driver output 30 LVG3 Analog Out Phase 3 low-side driver output 31 RES4 Reserved Pin must be left floating Phase 1 high-side (floating) common 33 OUT1 Power voltage 34 HVG1(1) Analog Out Phase 1 high-side driver output 35 BOOT1 Power Phase 1 bootstrap supply voltage Phase 2 high-side (floating) common 40 OUT2 Power voltage 41 HVG2(1) Analog Out Phase 2 high-side driver output 42 BOOT2 Power Phase 2 bootstrap supply voltage Phase 3 high-side (floating) common 46 OUT3 Power voltage 47 HVG3(1) Analog Out Phase 3 high-side driver output 48 BOOT3 Power Phase 3 bootstrap supply voltage 50 RES5 Reserved Pin must be left floating 51 VCC Power Driver low-side and logic supply voltage 52 RES1 Reserved Pin must be left floating 53 RES2 Reserved Pin must be left floating 54 RES3 Reserved Pin must be left floating 55 PA12 I/O - FT MCU PA12 6/29 DS13048 Rev 2 Document Outline 1 Block diagram Figure 1. STSPIN32F025x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F025x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F025x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history