Datasheet PT7C4363BQ (Diodes) - 9

PT7C4363BQ Function Description Overview of Functions 1. Clock Function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
2. Alarm Function
These devices have one alarm system that outputs interrupt signals from INT for PT7C4363BQ to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm.
3. Programmable Square Wave Output
A square wave output enable bit controls square wave output at pin 7. Four frequencies are selectable: 1, 32, 1.024k, and 32.768kHz.
4. Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pul -up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.
5. Oscillator Fail Detect
When oscillator fail, OSF bit will be set.
6. Oscillator Enable/Disable
Only time count chain can be enable or disable by STOP bit.
7. Timer Function
The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1/60 Hz) and enables or disables the timer. The timer counts down from software loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned.
8. Reset Function
The PT7C4363BQ includes an internal reset circuit which is active whenever the oscil ator is stopped. In the reset state the I2C- bus logic is initialized and al registers, including the address pointer, are cleared with the exception of bits FE, OSF, TD1, TD0, TESTC and AE which are set to logic 1. PT7C4363BQ
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July 2019 Document Number DS42042 Rev 1-2 9 © Diodes Incorporated Document Outline Features Description Pin Configuration Pin Description Function Block Maximum Ratings Recommended Operating Conditions DC Electrical Characteristics AC Electrical Characteristics Recommended Layout for Crystal Cpar is all parasitical capacitor between X1 and X2. Crystal Specifications Function Description Overview of Functions Registers Control and Status Register Time Counter Days of the Week Counter Calendar Counter AE W4 Communication I2C Bus Interface Overview of I2C-BUS System Configuration Starting and Stopping I2C Bus Communications Slave Address Part Marking Mechanical Information