Datasheet SiC476, SiC477, SiC478, SiC479 (Vishay) - 8

SiC476, SiC477, SiC478, SiC479
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Output Undervoltage Protection (UVP) Pre-Bias Start-Up
UVP is implemented by monitoring output through VFB pin. In case of pre-bias startup, if the sensed voltage on FB is If the voltage level at VFB goes below 0.16 V (VOUT is 20 % higher than the internal soft-start ramp value, control logic of VOUT set point) for more than 25 μs a UVP event is prevents HS and LS FET from switching to avoid negative recognized and both HS and LS MOSFETs are turned off. output voltage spike and excessive current sinking through After a time-out period equal to 20 soft start cycles, the IC LS FET. attempts to re-start by going through a soft start cycle. If the fault condition still exists, the above cycle will be repeated. UVP is only active after the completion of soft-start sequence.
Output Over Voltage Protection (OVP)
For OVP implementation, output is monitored through FB pin. After soft start, if the voltage level at FB is above 0.96 V (typ.) (VOUT is 120 % of VOUT set point), OVP is triggered with both the HS and LS MOSFETs turned off. Normal operation is resumed once FB voltage drops back to 0.96 V. OVP is active immediately after VDD passes UVLO level.
Over Temperature Protection (OTP)
SiC47x has internal thermal monitor block that turns off both
Fig. 7 - Pre-Bias Start-Up
HS and LS FETs when junction temperature is above 150 °C
Power Good
(typ). A hysteresis of 35 °C is implemented, so when junction temperature drops below 115 °C, the device restarts by SiC47x’s power good is an open-drain output. Pull PGOOD initiating soft-start sequence again. pin high up to 5 V through a 10K resistor to use this signal. Power good window is shown in the Fig. 8. If voltage level
Sequencing of Input / Output Supplies
on FB pin is out of this window, PG signal is de-asserted by SiC47x has no sequencing requirements on any of its pulling down to GND. To prevent false triggering during input / output (VIN, VDRV, VDD, VCIN, EN) supplies or enables. transient events, PGOOD has a 25 μs blanking time.
Enable
The SiC47x has an enable pin to turn the part on and off. Driving this pin high enables the device, while grounding it VFB_Rising_Vth_OV turns it off. (typ. = 0.96 V) VFB_Falling_Vth_OV The SiC47x enable has a weak pull down to prevent (typ. = 0.91 V) V unwanted turn on due to a floating GPIO. ref (0.8 V) VFB_Falling_Vth_UV There are no sequencing requirements with respect to other V (typ. = 0.72 V) VFB_Rising_Vth_UV FB input / output supplies. (typ. = 0.77 V)
Soft-Start
Pull-high During soft start time period, inrush current is limited and the PG output voltage is ramped gradually. The following control scheme is implemented: Once the V Pull-low DD voltage reaches the UVLO trip point, an internal “Soft start Reference” (SR) begins to ramp up. The
Fig. 8 - PGOOD Window and Timing Diagram
SR ramp rate is determined by the external soft start capacitor. There is an internal 5 μA current source tied to the soft start pin which charges the external soft start cap. The internal SR signal is being used as a reference voltage to the loop error amplifier (see functional block diagram). The control scheme guarantees that the output voltage during the soft start interval will ramp up coincidently with the SR signal. voltage. The speed of the internal soft start ramp can SiC47x soft-start time is adjustable by selecting a capacitor value from the following equation. C x 0.8 V SS time ext = ---------------- 5 μA During soft-start period, OCP is activated. Short circuit protection is not active until soft-start is complete. S19-0910-Rev. C, 28-Oct-2019
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