Data Brief AK8464 (Asahi Kasei Microdevices) - 10
| Fabricante | Asahi Kasei Microdevices |
| Descripción | 3ch input 10bit 35MSPS/ch AFE for MFP or CIS module with CCDI/F, TG, LVDS, LDO, Synth_PLL, and SSCG_PLL |
| Páginas / Página | 13 / 10 — Product Brief. 5.2. Pin Functions |
| Formato / tamaño de archivo | PDF / 341 Kb |
| Idioma del documento | Inglés |
Product Brief. 5.2. Pin Functions
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Product Brief
[AK8464]
5.2. Pin Functions
Reset [SRSTN] No Pin Name IO Description State (*1) (*2) 1 CCDIN0 I --- --- Sensor signal input CH0 2 AVDD33 P --- --- Analog Power Supply 3.3V 3 CCDIN1 I --- --- Sensor signal input CH1 Test pin (must be fixed to Low) 4 TEST0 I --- --- This pin is internally pulled-down by 100kΩ. 5 CCDIN2 I --- --- Sensor signal input CH2 Reset signal input 6 RESETB I --- --- This pin is internally pulled-down by 100kΩ. General Purpose Input/Output 7 PORT0 IO --- --- This pin becomes input during reset. It is internally pulled-down by 100kΩ. General Purpose Input/Output 8 PORT1 IO --- --- This pin becomes input during reset. It is internally pulled-down by 100kΩ. Test pin (must be fixed to Low) 9 TEST1 I --- --- This pin is internally pulled-down by 100kΩ. Synchronize signal Input/Output for Main Scanning 10 TRIG IO --- --- This pin becomes input during reset. It is internally pulled-down by 100kΩ. LDO Output 1.8V is generated from SVDD33 and output. 11 LDOS O Low Low Connect a 1.0uF capacitor between this pin and VSS. This pin is internally pulled-down when [NPD] = 0. 12 SVDD33 P --- --- Power Supply for LDO 3.3V CP Output of SSCG_PLL Connect R, C1 and C2 between this pin and VSS. 13 PLL_LPF IO Low Low This pin is internally pulled-down when [NPD] = 0. Parasitic capacity of the board connected to PLL_LPF must be less than 10pF when [SSCG_ON] = 0. LDO Output 1.8V is generated from SVDD33 and output. 14 LDODSS0 O Low 1.8V Connect a 1.0uF capacitor between this pin and VSS. This pin is internally pulled-down during reset. LDO Output 1.8V is generated from SVDD33 and output. 15 LDODSS1 O Low 1.8V Connect a 1.0uF capacitor between this pin and VSS. This pin is internally pulled-down during reset. 16 TG0 O Low Low TG Output 17 TG1 O Low Low TG Output 18 TG2 O Low Low TG Output 19 TG3 O Low Low TG Output 20 SPL O Low Low AFE Sampling signal Output, Internal signal Monitor pin 21 TVDD33 P --- --- TG Input/Output Buffer Power 3.3V 22 TG4 O Low Low TG Output 23 TG5 O Low Low TG Output 24 TG6 O Low Low TG Output 25 TG7 O Low Low TG Output 26 TG8 O Low Low TG Output 27 TG9 O Low Low TG Output 28 TG10 O Low Low TG Output 29 TG11 O Low Low TG Output 30 TVDD33 P --- --- TG Input/Output Buffer Power 3.3V 31 LVDO4N O High-Z High-Z LVDS Data Output Rev.1.00E 2019/6 - 10 -
[AK8464]
5.2. Pin Functions
Reset [SRSTN] No Pin Name IO Description State (*1) (*2) 1 CCDIN0 I --- --- Sensor signal input CH0 2 AVDD33 P --- --- Analog Power Supply 3.3V 3 CCDIN1 I --- --- Sensor signal input CH1 Test pin (must be fixed to Low) 4 TEST0 I --- --- This pin is internally pulled-down by 100kΩ. 5 CCDIN2 I --- --- Sensor signal input CH2 Reset signal input 6 RESETB I --- --- This pin is internally pulled-down by 100kΩ. General Purpose Input/Output 7 PORT0 IO --- --- This pin becomes input during reset. It is internally pulled-down by 100kΩ. General Purpose Input/Output 8 PORT1 IO --- --- This pin becomes input during reset. It is internally pulled-down by 100kΩ. Test pin (must be fixed to Low) 9 TEST1 I --- --- This pin is internally pulled-down by 100kΩ. Synchronize signal Input/Output for Main Scanning 10 TRIG IO --- --- This pin becomes input during reset. It is internally pulled-down by 100kΩ. LDO Output 1.8V is generated from SVDD33 and output. 11 LDOS O Low Low Connect a 1.0uF capacitor between this pin and VSS. This pin is internally pulled-down when [NPD] = 0. 12 SVDD33 P --- --- Power Supply for LDO 3.3V CP Output of SSCG_PLL Connect R, C1 and C2 between this pin and VSS. 13 PLL_LPF IO Low Low This pin is internally pulled-down when [NPD] = 0. Parasitic capacity of the board connected to PLL_LPF must be less than 10pF when [SSCG_ON] = 0. LDO Output 1.8V is generated from SVDD33 and output. 14 LDODSS0 O Low 1.8V Connect a 1.0uF capacitor between this pin and VSS. This pin is internally pulled-down during reset. LDO Output 1.8V is generated from SVDD33 and output. 15 LDODSS1 O Low 1.8V Connect a 1.0uF capacitor between this pin and VSS. This pin is internally pulled-down during reset. 16 TG0 O Low Low TG Output 17 TG1 O Low Low TG Output 18 TG2 O Low Low TG Output 19 TG3 O Low Low TG Output 20 SPL O Low Low AFE Sampling signal Output, Internal signal Monitor pin 21 TVDD33 P --- --- TG Input/Output Buffer Power 3.3V 22 TG4 O Low Low TG Output 23 TG5 O Low Low TG Output 24 TG6 O Low Low TG Output 25 TG7 O Low Low TG Output 26 TG8 O Low Low TG Output 27 TG9 O Low Low TG Output 28 TG10 O Low Low TG Output 29 TG11 O Low Low TG Output 30 TVDD33 P --- --- TG Input/Output Buffer Power 3.3V 31 LVDO4N O High-Z High-Z LVDS Data Output Rev.1.00E 2019/6 - 10 -