Datasheet ARG81800 (Allegro) - 6

40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS: Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT VOLTAGE
Input Voltage Range VIN VIN must first rise above VINUV(ON) (max) 3.5 – 36 V VIN UVLO Start VINUV(ON) VIN rising 3.35 3.55 3.8 V VIN UVLO Stop VINUV(OFF) VIN falling 3.1 3.3 3.5 V VIN UVLO Hysteresis VINUV(HYS) − 250 − mV
INPUT SUPPLY CURRENT
Input Shutdown Current [2] IIN(SD) VIN = 12 V, VEN = 0, VSW = VIN, TJ = 25°C − 1 2 µA Input Current, PWM Mode [2] IIN(PWM) VIN = 12 V, VEN = 2 V, no load, no switching − 5 6.5 mA V 3.3 V IN = 12 V, IOUT = 0 µA, TJ = 25°C − 8 − µA OUT LP Input Current [3][4] ILP(3.3V) VIN = 12 V, IOUT = 50 µA, TJ = 25°C − 33 − µA V 5.0 V IN = 12 V, IOUT = 0 µA, TJ = 25°C − 8 − µA OUT LP Input Current [3][4] ILP(5.0V) VIN = 12 V, IOUT = 50 µA, TJ = 25°C − 44 − µA
REGULATION ACCURACY (FB PIN)
Feedback Voltage Accuracy VFB –40°C < TJ < 150°C, VIN ≥ 3.5 V, VFB = VCOMP 788 800 812 mV
SWITCHING FREQUENCY AND DITHERING (FSET PIN)
RFSET = 14.3 kΩ 1.93 2.15 2.37 MHz R PWM Switching Frequency f FSET = 34 kΩ 0.90 1.00 1.10 MHz SW RFSET = 71.5 kΩ 450 500 550 kHz RFSET = 86.6 kΩ 360 410 460 kHz Dropout Switching Frequency fDROP − fSW/4 − − CLK PWM Frequency Dither Range f OUT left open − ±5 ±6.5 % of fSW DITH(RNG) CLKOUT connected to VREG − 0 − % of fSW PWM Dither Modulation Frequency fDITH(MAG) − ±0.5 − % of fSW
PULSE WIDTH MODULATION (PWM) TIMING AND CONTROL
Minimum Controllable SW On-Time tON(MIN) VIN = 12 V, IOUT = 0.7 A, VBOOT – VSW = 4.5 V − 60 85 ns Minimum SW Off-Time tOFF(MIN) VIN =12 V, IOUT = 0.7 A − 85 110 ns gm COMP to SW Current Gain POWER1 ARG81800 − 2.0 − A/V gmPOWER2 ARG81800-1 − 1.0 − A/V SE1 fSW = 2.15 MHz, ARG81800 650 900 1100 mA/µs S Slope Compensation E2 fSW = 2.15 MHz, ARG81800-1 325 450 550 mA/µs SE3 fSW = 252 kHz, ARG81800 75 100 125 mA/µs SE4 fSW = 252 kHz, ARG81800-1 35 50 65 mA/µs PWM Ramp Offset VPWM(OFFS) − 650 − mV Continued on next page... 6 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing