Datasheet STA559BW (STMicroelectronics) - 8
| Fabricante | STMicroelectronics |
| Descripción | 5 V, 2 A, 2.1 channel high-efficiency digital audio system Sound Terminal |
| Páginas / Página | 67 / 8 — Description. STA559BW. 1 Description. Figure 1. Block diagram. Digital … |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
Description. STA559BW. 1 Description. Figure 1. Block diagram. Digital DSP. Power
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Description STA559BW 1 Description
The STA559BW is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor. The STA559BW is part of the Sound Terminal® family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. The power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. For example, 2.1 channels can be provided by two half bridges and a single full bridge, supplying up to 2 x 1.4 W + 1 x 6 W of output power or two channels can be provided by two full-bridges, supplying up to 2 x 3 W of output power. The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device plus a drive for an external FFX power amplifier, such as STA533WF or STA515W. Also provided in the STA559BW are a full assortment of digital processing features. This includes up to four programmable biquads (EQ) per channel. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes.
Figure 1. Block diagram
I²C Protection current/thermal I²S Channel interface 1A Channel Logic Power 1B Volume control control FFX Channel 2A Regulators Channel PLL 2B Bias
Digital DSP Power
8/67 DocID18190 Rev 3 Document Outline Table 1. Device summary 1 Description Figure 1. Block diagram 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) 2.2 Pin description Table 2. Pin description 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings 3.2 Thermal data Table 4. Thermal data 3.3 Recommended operating conditions Table 5. Recommended operating condition 3.4 Electrical specifications for the digital section Table 6. Electrical specifications - digital section 3.5 Electrical specifications for the power section Table 7. Electrical specifications - power section Figure 3. Test circuit 3.6 Power on/off sequence Figure 4. Power-on sequence Figure 5. Power-off sequence for pop-free turn-off 4 Processing data paths Figure 6. Left and right processing 5 I²C bus specification 5.1 Communication protocol 5.1.1 Data transition or change 5.1.2 Start condition 5.1.3 Stop condition 5.1.4 Data input 5.2 Device addressing 5.3 Write operation 5.3.1 Byte write 5.3.2 Multi-byte write Figure 7. Write mode sequence 5.4 Read operation 5.4.1 Current address byte read 5.4.2 Current address multi-byte read 5.4.3 Random address byte read 5.4.4 Random address multi-byte read Figure 8. Read mode sequence 6 Register description Table 8. Register summary 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00) Table 9. Master clock select Table 10. Input sampling rates Table 11. Internal interpolation ratio Table 12. IR bit settings as a function of input sample rate Table 13. Thermal warning recovery bypass Table 14. Thermal warning adjustment bypass Table 15. Fault detect recovery bypass 6.1.2 Configuration register B (addr 0x01) Table 16. Serial audio input interface Table 17. Serial data first bit Table 18. Support serial audio input formats for MSB-first Table 19. Supported serial audio input formats for LSB-first Table 20. Delay serial clock enable Table 21. Channel input mapping 6.1.3 Configuration register C (addr 0x02) Table 22. FFX power output mode Table 23. FFX compensating pulse size bits Table 24. Compensating pulse size Table 25. Overcurrent warning bypass 6.1.4 Configuration register D (addr 0x03) Table 26. High-pass filter bypass Table 27. De-emphasis Table 28. DSP bypass Table 29. Postscale link Table 30. Biquad coefficient link Table 31. Dynamic range compression/anti-clipping bit Table 32. Zero-detect mute enable Table 33. Submix mode enable 6.1.5 Configuration register E (addr 0x04) Table 34. Max power correction variable Table 35. Max power correction Table 36. Noise-shaper bandwidth selection Table 37. AM mode enable Table 38. PWM speed mode Table 39. Distortion compensation variable enable Table 40. Zero-crossing volume enable Table 41. Soft volume update enable 6.1.6 Configuration register F (addr 0x05) Table 42. Output configuration Table 43. Output configuration engine selection Figure 9. OCFG = 00 (default value) Figure 10. OCFG = 01 Figure 11. OCFG = 10 Figure 12. OCFG = 11 Figure 13. Output mapping scheme Figure 14. 2.0 channels (OCFG = 00) PWM slots Figure 15. 2.1 channels (OCFG = 01) PWM slots Figure 16. 2.1 channels (OCFG = 10) PWM slots Table 44. Invalid input detect mute enable Table 45. Binary output mode clock loss detection Table 46. LRCK double trigger protection Table 47. Auto EAPD on clock loss Table 48. IC power down Table 49. External amplifier power down 6.2 Volume control registers (addr 0x06 - 0x0A) 6.2.1 Mute/line output configuration register (addr 0x06) Table 50. Line output configuration 6.2.2 Master volume register (addr 0x07) Table 51. Master volume offset as a function of MVOL 6.2.3 Channel 1 volume (addr 0x08) 6.2.4 Channel 2 volume (addr 0x09) 6.2.5 Channel 3 / line output volume (addr 0x0A) Table 52. Channel volume as a function of CxVOL 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B) Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00 6.3.2 Audio preset register 2 (addr 0x0C) Table 54. AM interference frequency switching bits Table 55. Audio preset AM switching frequency selection Table 56. Bass management crossover Table 57. Bass management crossover frequency 6.4 Channel configuration registers (addr 0x0E - 0x10) Table 58. Tone control bypass Table 59. EQ bypass Table 60. Volume bypass register Table 61. Binary output enable registers Table 62. Channel limiter mapping as a function of CxLS bits Table 63. Channel output mapping as a function of CxOM bits 6.5 Tone control register (addr 0x11) Table 64. Tone control boost/cut as a function of BTC and TTC bits 6.6 Dynamic control registers (addr 0x12 - 0x15) 6.6.1 Limiter 1 attack/release rate (addr 0x12) 6.6.2 Limiter 1 attack/release threshold (addr 0x13) 6.6.3 Limiter 2 attack/release rate (addr 0x14) 6.6.4 Limiter 2 attack/release threshold (addr 0x15) 6.6.5 Description Figure 17. Basic limiter and volume flow diagram Table 65. Limiter attack rate vs LxA bits Table 66. Limiter release rate vs LxR bits Table 67. Limiter attack threshold vs LxAT bits (AC mode) Table 68. Limiter release threshold vs LxRT bits (AC mode) Table 69. Limiter attack threshold vs LxAT bits (DRC mode) Table 70. Limiter release threshold vs LxRT bits (DRC mode) 6.7 User-defined coefficient control registers (addr 0x16 - 0x26) 6.7.1 Coefficient address register (addr 0x16) 6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) 6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) 6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) 6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) 6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) 6.7.7 Coefficient read/write control register (addr 0x26) 6.7.8 Description Table 71. RAM block for biquads, mixing, scaling, bass management 6.8 Variable max power correction registers (addr 0x27 - 0x28) 6.9 Distortion compensation registers (addr 0x29 - 0x2A) 6.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) 6.11 Device status register (addr 0x2D) 7 Applications 7.1 Applications schematic 7.2 PLL filter circuit 7.3 Typical output configuration Figure 18. Output configuration for stereo BTL mode (RL = 8 W) Figure 19. Applications circuit 8 Package thermal characteristics Figure 20. PowerSSO-36 power derating curve 9 Package mechanical data Table 72. PowerSSO-36 EPD dimensions Figure 21. PowerSSO-36 EPD outline drawing 10 Revision history Table 73. Document revision history
The STA559BW is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor. The STA559BW is part of the Sound Terminal® family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. The power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. For example, 2.1 channels can be provided by two half bridges and a single full bridge, supplying up to 2 x 1.4 W + 1 x 6 W of output power or two channels can be provided by two full-bridges, supplying up to 2 x 3 W of output power. The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device plus a drive for an external FFX power amplifier, such as STA533WF or STA515W. Also provided in the STA559BW are a full assortment of digital processing features. This includes up to four programmable biquads (EQ) per channel. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes.
Figure 1. Block diagram
I²C Protection current/thermal I²S Channel interface 1A Channel Logic Power 1B Volume control control FFX Channel 2A Regulators Channel PLL 2B Bias
Digital DSP Power
8/67 DocID18190 Rev 3 Document Outline Table 1. Device summary 1 Description Figure 1. Block diagram 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) 2.2 Pin description Table 2. Pin description 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings 3.2 Thermal data Table 4. Thermal data 3.3 Recommended operating conditions Table 5. Recommended operating condition 3.4 Electrical specifications for the digital section Table 6. Electrical specifications - digital section 3.5 Electrical specifications for the power section Table 7. Electrical specifications - power section Figure 3. Test circuit 3.6 Power on/off sequence Figure 4. Power-on sequence Figure 5. Power-off sequence for pop-free turn-off 4 Processing data paths Figure 6. Left and right processing 5 I²C bus specification 5.1 Communication protocol 5.1.1 Data transition or change 5.1.2 Start condition 5.1.3 Stop condition 5.1.4 Data input 5.2 Device addressing 5.3 Write operation 5.3.1 Byte write 5.3.2 Multi-byte write Figure 7. Write mode sequence 5.4 Read operation 5.4.1 Current address byte read 5.4.2 Current address multi-byte read 5.4.3 Random address byte read 5.4.4 Random address multi-byte read Figure 8. Read mode sequence 6 Register description Table 8. Register summary 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00) Table 9. Master clock select Table 10. Input sampling rates Table 11. Internal interpolation ratio Table 12. IR bit settings as a function of input sample rate Table 13. Thermal warning recovery bypass Table 14. Thermal warning adjustment bypass Table 15. Fault detect recovery bypass 6.1.2 Configuration register B (addr 0x01) Table 16. Serial audio input interface Table 17. Serial data first bit Table 18. Support serial audio input formats for MSB-first Table 19. Supported serial audio input formats for LSB-first Table 20. Delay serial clock enable Table 21. Channel input mapping 6.1.3 Configuration register C (addr 0x02) Table 22. FFX power output mode Table 23. FFX compensating pulse size bits Table 24. Compensating pulse size Table 25. Overcurrent warning bypass 6.1.4 Configuration register D (addr 0x03) Table 26. High-pass filter bypass Table 27. De-emphasis Table 28. DSP bypass Table 29. Postscale link Table 30. Biquad coefficient link Table 31. Dynamic range compression/anti-clipping bit Table 32. Zero-detect mute enable Table 33. Submix mode enable 6.1.5 Configuration register E (addr 0x04) Table 34. Max power correction variable Table 35. Max power correction Table 36. Noise-shaper bandwidth selection Table 37. AM mode enable Table 38. PWM speed mode Table 39. Distortion compensation variable enable Table 40. Zero-crossing volume enable Table 41. Soft volume update enable 6.1.6 Configuration register F (addr 0x05) Table 42. Output configuration Table 43. Output configuration engine selection Figure 9. OCFG = 00 (default value) Figure 10. OCFG = 01 Figure 11. OCFG = 10 Figure 12. OCFG = 11 Figure 13. Output mapping scheme Figure 14. 2.0 channels (OCFG = 00) PWM slots Figure 15. 2.1 channels (OCFG = 01) PWM slots Figure 16. 2.1 channels (OCFG = 10) PWM slots Table 44. Invalid input detect mute enable Table 45. Binary output mode clock loss detection Table 46. LRCK double trigger protection Table 47. Auto EAPD on clock loss Table 48. IC power down Table 49. External amplifier power down 6.2 Volume control registers (addr 0x06 - 0x0A) 6.2.1 Mute/line output configuration register (addr 0x06) Table 50. Line output configuration 6.2.2 Master volume register (addr 0x07) Table 51. Master volume offset as a function of MVOL 6.2.3 Channel 1 volume (addr 0x08) 6.2.4 Channel 2 volume (addr 0x09) 6.2.5 Channel 3 / line output volume (addr 0x0A) Table 52. Channel volume as a function of CxVOL 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B) Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00 6.3.2 Audio preset register 2 (addr 0x0C) Table 54. AM interference frequency switching bits Table 55. Audio preset AM switching frequency selection Table 56. Bass management crossover Table 57. Bass management crossover frequency 6.4 Channel configuration registers (addr 0x0E - 0x10) Table 58. Tone control bypass Table 59. EQ bypass Table 60. Volume bypass register Table 61. Binary output enable registers Table 62. Channel limiter mapping as a function of CxLS bits Table 63. Channel output mapping as a function of CxOM bits 6.5 Tone control register (addr 0x11) Table 64. Tone control boost/cut as a function of BTC and TTC bits 6.6 Dynamic control registers (addr 0x12 - 0x15) 6.6.1 Limiter 1 attack/release rate (addr 0x12) 6.6.2 Limiter 1 attack/release threshold (addr 0x13) 6.6.3 Limiter 2 attack/release rate (addr 0x14) 6.6.4 Limiter 2 attack/release threshold (addr 0x15) 6.6.5 Description Figure 17. Basic limiter and volume flow diagram Table 65. Limiter attack rate vs LxA bits Table 66. Limiter release rate vs LxR bits Table 67. Limiter attack threshold vs LxAT bits (AC mode) Table 68. Limiter release threshold vs LxRT bits (AC mode) Table 69. Limiter attack threshold vs LxAT bits (DRC mode) Table 70. Limiter release threshold vs LxRT bits (DRC mode) 6.7 User-defined coefficient control registers (addr 0x16 - 0x26) 6.7.1 Coefficient address register (addr 0x16) 6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) 6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) 6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) 6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) 6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) 6.7.7 Coefficient read/write control register (addr 0x26) 6.7.8 Description Table 71. RAM block for biquads, mixing, scaling, bass management 6.8 Variable max power correction registers (addr 0x27 - 0x28) 6.9 Distortion compensation registers (addr 0x29 - 0x2A) 6.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) 6.11 Device status register (addr 0x2D) 7 Applications 7.1 Applications schematic 7.2 PLL filter circuit 7.3 Typical output configuration Figure 18. Output configuration for stereo BTL mode (RL = 8 W) Figure 19. Applications circuit 8 Package thermal characteristics Figure 20. PowerSSO-36 power derating curve 9 Package mechanical data Table 72. PowerSSO-36 EPD dimensions Figure 21. PowerSSO-36 EPD outline drawing 10 Revision history Table 73. Document revision history