Datasheet PIC18(L)F2X/4X/5XK42 (Microchip)
| Fabricante | Microchip |
| Descripción | Highly Integrated 8-Bit PIC Microcontrollers in 28-to 48-Pins |
| Páginas / Página | 18 / 1 — PIC18(L)F2X/4X/5XK42. Highly Integrated 8-Bit PIC® Microcontrollers in … |
| Formato / tamaño de archivo | PDF / 208 Kb |
| Idioma del documento | Inglés |
PIC18(L)F2X/4X/5XK42. Highly Integrated 8-Bit PIC® Microcontrollers in 28- to 48- Pins. Description. Core Features
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Versión de texto del documento
PIC18(L)F2X/4X/5XK42 Highly Integrated 8-Bit PIC® Microcontrollers in 28- to 48- Pins Description
The PIC18(L)F2X/4X/5XK42 microcontroller family is available in 28/40/44/48-pin devices. This family features a 12-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and threshold comparison. Additionally, Vectored Interrupt Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with support for Asynchronous, DMX, DALI and LIN protocols, SPI, I2C, memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.
Core Features Operating Characteristics
• C Compiler Optimized RISC Architecture • Operating Voltage Range: • Operating Speed: - 1.8V to 3.6V (PIC18LF2X/4X/5XK42) - Up to 64 MHz clock input - 2.3V to 5.5V (PIC18F2X/4X/5XK42) - 62.5 ns minimum instruction cycle • Temperature Range: • Two Direct Memory Access (DMA) Controllers: - Industrial: -40°C to 85°C - Data transfers to SFR/GPR spaces from - Extended: -40°C to 125°C either Program Flash Memory, Data
Power-Saving Functionality
EEPROM or SFR/GPR spaces - User programmable source and destination • DOZE mode: Ability to run CPU core slower than sizes the system clock - Hardware and software triggered data • IDLE mode: Ability to halt CPU core while internal transfers peripherals continue operating • Vectored Interrupt Capability: • Sleep mode: Lowest power consumption - Selectable high/low priority • Peripheral Module Disable (PMD): - Fixed Interrupt latency - Ability to disable peripherals to minimize power - Programmable vector table base address consumption • 31-Level Deep Hardware Stack • Low-Current Power-on Reset (POR)
eXtreme Low-Power (XLP) Features
• Configurable Power-up Timer (PWRTE) • Sleep mode: 50 nA @ 1.8V, typical • Brown-Out Reset (BOR) • Watchdog Timer: 500 nA @ 1.8V, typical • Low-Power BOR (LPBOR) Option • Secondary Oscillator: 500 nA @ 32 kHz • Windowed Watchdog Timer (WWDT): • Operating Current: - Variable prescaler selection - 8 uA @ 32 kHz, 1.8V, typical - Variable window size selection - 32 uA/MHz @ 1.8V, typical - Configurable in hardware or software • Programmable Code Protection:
Digital Peripherals
- Configurable Boot and App region sizes • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Memory
• Four 16-Bit Timers (TMR0/1/3/5) • Up to 128 KB Flash Program Memory • Four Configurable Logic Cell (CLC): • Up to 8 KB Data SRAM Memory - Integrated combinational and sequential logic • Up to 1 KB Data EEPROM • Three Complementary Waveform Generators • Memory Access Partition (MAP): (CWGs): - Bootloader write-protect - Rising and falling edge dead-band control - Configurable partition - Full-bridge, half-bridge, 1-channel drive • Device Information Area (DIA) Stores: - Multiple signal sources - Temp sensor factory calibrated data - Programmable dead band - Fixed Voltage Reference - Fault-shutdown input - Device ID • Four 16-Bit Capture/Compare/16-Bit PWM (CCP) modules • Four 10-bit Pulse Width Modulators (PWMs) 2016 Microchip Technology Inc.
Advance Information
DS40001861B-page 1 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Continued) Analog Peripherals Flexible Oscillator Structure TABLE 1: PIC18(L)F2X/4X/5XK42 Family Types TABLE 2: Packages FIGURE 1: 28-Pin SPDIP, SOIC, SSOP for PIC18(L)F2XK42 FIGURE 2: 28-Pin UQFN (4x4) for PIC18(L)F2XK42 FIGURE 3: 28-Pin QFN (6x6x0.9 mm) for PIC18(L)F2XK42 FIGURE 4: 40-Pin PDIP for PIC18(L)F4XK42 FIGURE 5: 40-Pin UQFN (5x5x0.5 mm) for PIC18(L)F4XK42 FIGURE 6: 44-Pin QFN (8x8x0.9 mm) for PIC18(L)F5XK42 FIGURE 7: 44-Pin TQFP For PIC18(L)F4XK42 FIGURE 8: 48-Pin TQFP/UQFN for PIC18(L)F5XK42 TABLE 3: 28-Pin Allocation Table (PIC18(L)F2XK42) TABLE 4: 40/44-Pin Allocation Table For PIC18(L)F4XK42, PIC18(L)F5XK42 TABLE 5: 48-Pin Allocation Table for PIC18(L)F5XK42 Trademarks Worldwide Sales
The PIC18(L)F2X/4X/5XK42 microcontroller family is available in 28/40/44/48-pin devices. This family features a 12-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and threshold comparison. Additionally, Vectored Interrupt Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with support for Asynchronous, DMX, DALI and LIN protocols, SPI, I2C, memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.
Core Features Operating Characteristics
• C Compiler Optimized RISC Architecture • Operating Voltage Range: • Operating Speed: - 1.8V to 3.6V (PIC18LF2X/4X/5XK42) - Up to 64 MHz clock input - 2.3V to 5.5V (PIC18F2X/4X/5XK42) - 62.5 ns minimum instruction cycle • Temperature Range: • Two Direct Memory Access (DMA) Controllers: - Industrial: -40°C to 85°C - Data transfers to SFR/GPR spaces from - Extended: -40°C to 125°C either Program Flash Memory, Data
Power-Saving Functionality
EEPROM or SFR/GPR spaces - User programmable source and destination • DOZE mode: Ability to run CPU core slower than sizes the system clock - Hardware and software triggered data • IDLE mode: Ability to halt CPU core while internal transfers peripherals continue operating • Vectored Interrupt Capability: • Sleep mode: Lowest power consumption - Selectable high/low priority • Peripheral Module Disable (PMD): - Fixed Interrupt latency - Ability to disable peripherals to minimize power - Programmable vector table base address consumption • 31-Level Deep Hardware Stack • Low-Current Power-on Reset (POR)
eXtreme Low-Power (XLP) Features
• Configurable Power-up Timer (PWRTE) • Sleep mode: 50 nA @ 1.8V, typical • Brown-Out Reset (BOR) • Watchdog Timer: 500 nA @ 1.8V, typical • Low-Power BOR (LPBOR) Option • Secondary Oscillator: 500 nA @ 32 kHz • Windowed Watchdog Timer (WWDT): • Operating Current: - Variable prescaler selection - 8 uA @ 32 kHz, 1.8V, typical - Variable window size selection - 32 uA/MHz @ 1.8V, typical - Configurable in hardware or software • Programmable Code Protection:
Digital Peripherals
- Configurable Boot and App region sizes • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Memory
• Four 16-Bit Timers (TMR0/1/3/5) • Up to 128 KB Flash Program Memory • Four Configurable Logic Cell (CLC): • Up to 8 KB Data SRAM Memory - Integrated combinational and sequential logic • Up to 1 KB Data EEPROM • Three Complementary Waveform Generators • Memory Access Partition (MAP): (CWGs): - Bootloader write-protect - Rising and falling edge dead-band control - Configurable partition - Full-bridge, half-bridge, 1-channel drive • Device Information Area (DIA) Stores: - Multiple signal sources - Temp sensor factory calibrated data - Programmable dead band - Fixed Voltage Reference - Fault-shutdown input - Device ID • Four 16-Bit Capture/Compare/16-Bit PWM (CCP) modules • Four 10-bit Pulse Width Modulators (PWMs) 2016 Microchip Technology Inc.
Advance Information
DS40001861B-page 1 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Continued) Analog Peripherals Flexible Oscillator Structure TABLE 1: PIC18(L)F2X/4X/5XK42 Family Types TABLE 2: Packages FIGURE 1: 28-Pin SPDIP, SOIC, SSOP for PIC18(L)F2XK42 FIGURE 2: 28-Pin UQFN (4x4) for PIC18(L)F2XK42 FIGURE 3: 28-Pin QFN (6x6x0.9 mm) for PIC18(L)F2XK42 FIGURE 4: 40-Pin PDIP for PIC18(L)F4XK42 FIGURE 5: 40-Pin UQFN (5x5x0.5 mm) for PIC18(L)F4XK42 FIGURE 6: 44-Pin QFN (8x8x0.9 mm) for PIC18(L)F5XK42 FIGURE 7: 44-Pin TQFP For PIC18(L)F4XK42 FIGURE 8: 48-Pin TQFP/UQFN for PIC18(L)F5XK42 TABLE 3: 28-Pin Allocation Table (PIC18(L)F2XK42) TABLE 4: 40/44-Pin Allocation Table For PIC18(L)F4XK42, PIC18(L)F5XK42 TABLE 5: 48-Pin Allocation Table for PIC18(L)F5XK42 Trademarks Worldwide Sales