Datasheet PIC18F27Q10, PIC18F47Q10 (Microchip) - 5

PIC18F27/47Q10 QFN VQFN QFN SPDIP SOIC SSOP TQFP PDIP Packages (ML) (STX) (MP) (SP) (SO) (SS) (PT) (P) (6x6x0.9) (4x4x1) (5x5x0.9)
PIC18F27Q10 ● ● ● ● ● PIC18F47Q10 ● ● ●
Important: 
Pin details are subject to change. Filename: 00-000028A.vsd Title: 28-pin DIP Last Edit: 10/3/2018 First Used: N/A
Pin Diagrams
Notes: Generic 28-pin dual in-line diagram
Figure 1. 28-pin SPDIP, SSOP, SOIC
Rev. 00-000028A 10/3/2018 MCLR/VPP/RE3 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 24 RB3 RA4 6 23 RB2 RA5 7 22 RB1 VSS 8 21 RB0 RA7 9 20 VDD RA6 10 19 VSS RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4
Figure 2. 28-pin QFN VQFN
P Rev. 00-000028B P T K 6/23/2017 L /V R DA C L P P C S /M /ICS /IC 1 0 3 7 6 5 4 A A E B B B B R R R R R R R 28 27 26 25 24 23 22 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 RA5 4 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 C C C C C C C R R R R R R R
Note: 
It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. © 2019 Microchip Technology Inc.
Datasheet
DS40002043D-page 5 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Operation Modes Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features PIC18F27/47Q10 Family Types Packages Pin Diagrams Pin Allocation Tables Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. Low-Power Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit Naming Conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 1.5. Register Legend 2. Guidelines for Getting Started with PIC18F27/47Q10 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. In-Circuit Serial Programming™ (ICSP™) Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Device Configuration 3.1. Configuration Words 3.2. Code Protection 3.2.1. Program Memory Protection 3.2.2. Data Memory Protection 3.3. Write Protection 3.4. User ID 3.5. Device ID and Revision ID 3.6. Register Summary - Configuration Words 3.7. Register Definitions: Configuration Words 3.7.1. CONFIG1 3.7.2. CONFIG2 3.7.3. CONFIG3 3.7.4. CONFIG4 3.7.5. CONFIG5 3.7.6. CONFIG6 3.8. Register Summary - Device and Revision 3.9. Register Definitions: Device and Revision 3.9.1. DEVICE ID 3.9.2. REVISION ID 4. OSC - Oscillator Module 4.1. Overview 4.2. Clock Source Types 4.2.1. External Clock Sources 4.2.1.1. EC Mode 4.2.1.2. LP, XT, HS Modes 4.2.1.3. Oscillator Start-up Timer (OST) 4.2.1.4. 4x PLL 4.2.1.5. Secondary Oscillator 4.2.2. Internal Clock Sources 4.2.2.1. HFINTOSC 4.2.2.2. MFINTOSC 4.2.2.3. LFINTOSC 4.2.2.4. ADCRC (also referred to as FRC) 4.2.3. Oscillator Status and Adjustments 4.2.3.1. Internal Oscillator Frequency Adjustment 4.2.3.2. Oscillator Status and Manual Enable 4.2.3.3. HFOR and MFOR Bits 4.3. Clock Switching 4.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 4.3.2. PLL Input Switch 4.3.3. Clock Switch and Sleep 4.4. Fail-Safe Clock Monitor 4.4.1. Fail-Safe Detection 4.4.2. Fail-Safe Operation 4.4.3. Fail-Safe Condition Clearing 4.4.4. Reset or Wake-up from Sleep 4.5. Register Summary - OSC 4.6. Register Definitions: Oscillator Control 4.6.1. OSCCON1 4.6.2. OSCCON2 4.6.3. OSCCON3 4.6.4. OSCSTAT 4.6.5. OSCFRQ 4.6.6. OSCTUNE 4.6.7. OSCEN 5. Reference Clock Output Module 5.1. Clock Source 5.1.1. Clock Synchronization 5.2. Programmable Clock Divider 5.3. Selectable Duty Cycle 5.4. Operation in Sleep Mode 5.5. Register Summary: Reference CLK 5.6. Register Definitions: Reference Clock 5.6.1. CLKRCON 5.6.2. CLKRCLK 6. Power-Saving Operation Modes 6.1. Doze Mode 6.1.1. Doze Operation 6.1.2. Interrupts During Doze 6.2. Sleep Mode 6.2.1. Wake-up from Sleep 6.2.2. Wake-up Using Interrupts 6.2.3. Low-Power Sleep Mode 6.2.3.1. Sleep Current vs. Wake-up Time 6.2.3.2. Peripheral Usage in Sleep 6.3. Idle Mode 6.3.1. Idle and Interrupts 6.3.2. Idle and WWDT 6.4. Peripheral Operation in Power-Saving Modes 6.5. Register Summary - Power Savings Control 6.6. Register Definitions: Power Savings Control 6.6.1. VREGCON 6.6.2. CPUDOZE 7. (PMD) Peripheral Module Disable 7.1. Disabling a Module 7.2. Enabling a Module 7.3. Register Summary - PMD 7.4. Register Definitions: Peripheral Module Disable 7.4.1. PMD0 7.4.2. PMD1 7.4.3. PMD2 7.4.4. PMD3 7.4.5. PMD4 7.4.6. PMD5 8. Resets 8.1. Power-on Reset (POR) 8.2. Brown-out Reset (BOR) 8.2.1. BOR is Always On 8.2.2. BOR is OFF in Sleep 8.2.3. BOR Controlled by Software 8.2.4. BOR and Bulk Erase 8.3. Low-Power Brown-out Reset (LPBOR) 8.3.1. Enabling LPBOR 8.3.1.1. LPBOR Module Output 8.4. MCLR Reset 8.4.1. MCLR Enabled 8.4.2. MCLR Disabled 8.5. Windowed Watchdog Timer (WWDT) Reset 8.6. RESET Instruction 8.7. Stack Overflow/Underflow Reset 8.8. Programming Mode Exit 8.9. Power-up Timer (PWRT) 8.10. Start-up Sequence 8.11. Determining the Cause of a Reset 8.12. Power Control (PCON0) Register 8.13. Register Summary - BOR Control and Power Control 8.14. Register Definitions: Power Control 8.14.1. BORCON 8.14.2. PCON0 8.14.3. PCON1 9. (WWDT) Windowed Watchdog Timer 9.1. Independent Clock Source 9.2. WWDT Operating Modes 9.2.1. WWDT Is Always On 9.2.2. WWDT Is Off in Sleep 9.2.3. WWDT Controlled by Software 9.3. Time-out Period 9.4. Watchdog Window 9.5. Clearing the WWDT 9.5.1. CLRWDT Considerations (Windowed Mode) 9.6. Operation During Sleep 9.7. Register Summary - WDT Control 9.8. Register Definitions: Windowed Watchdog Timer Control 9.8.1. WDTCON0 9.8.2. WDTCON1 9.8.3. WDTPSL 9.8.4. WDTPSH 9.8.5. WDTTMR 10. Memory Organization 10.1. Program Memory Organization 10.1.1. Program Counter 10.1.2. Return Address Stack 10.1.2.1. Top-of-Stack Access 10.1.2.2. Return Stack Pointer 10.1.2.3. Stack Overflow and Underflow Resets 10.1.2.4. PUSH and POP Instructions 10.1.2.5. Fast Register Stack 10.1.3. Look-up Tables in Program Memory 10.1.3.1. Computed GOTO 10.1.3.2. Table Reads and Table Writes 10.2. PIC18 Instruction Cycle 10.2.1. Clocking Scheme 10.2.2. Instruction Flow/Pipelining 10.2.3. Instructions in Program Memory 10.2.4. Two-Word Instructions 10.3. Data Memory Organization 10.3.1. Bank Select Register 10.3.2. Access Bank 10.3.3. General Purpose Register File 10.3.4. Special Function Registers 10.3.5. Status Register 10.4. Data Addressing Modes 10.4.1. Inherent and Literal Addressing 10.4.2. Direct Addressing 10.4.3. Indirect Addressing 10.4.3.1. FSR Registers and the INDF Operand 10.4.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 10.4.3.3. Operations by FSRs on FSRs 10.5. Data Memory and the Extended Instruction Set 10.5.1. Indexed Addressing with Literal Offset 10.5.2. Instructions Affected by Indexed Literal Offset Mode 10.5.3. Mapping the Access Bank in Indexed Literal Offset Mode 10.6. PIC18 Instruction Execution and the Extended Instruction Set 10.7. Register Summary: Memory and Status 10.8. Register Definitions: Memory and Status 10.8.1. PCL 10.8.2. PCLAT 10.8.3. TOS 10.8.4. STKPTR 10.8.5. STATUS 10.8.6. WREG 10.8.7. INDF 10.8.8. POSTDEC 10.8.9. POSTINC 10.8.10. PREINC 10.8.11. PLUSW 10.8.12. FSR 10.8.13. BSR 11. (NVM) Nonvolatile Memory Control 11.1. Program Flash Memory 11.1.1. Table Pointer Operations 11.1.1.1. Table Pointer Register 11.1.1.2. Table Latch Register 11.1.1.3. Table Read Operations 11.1.1.4. Table Write Operations 11.1.1.5. Table Pointer Boundaries 11.1.1.6. Reading the Program Flash Memory 11.1.2. NVM Unlock Sequence 11.1.3. Erasing Program Flash Memory (PFM) 11.1.3.1. PFM Erase Sequence 11.1.4. Writing to Program Flash Memory 11.1.4.1. PFM Sector Write Sequence 11.1.4.2. PFM Word Write Sequence 11.1.4.3. Write Verify 11.1.4.4. Unexpected Termination of Write Operation 11.1.4.5. Protection Against Spurious Writes 11.2. User ID, Device ID and Configuration Word Access 11.3. Data Flash Memory (DFM) 11.3.1. Reading the DFM 11.3.2. Writing to DFM 11.3.3. DFM Write Verify 11.3.4. Operation During Code-Protect and Write-Protect 11.3.5. Protection Against Spurious Write 11.3.6. Erasing the DFM 11.4. Register Summary: NVM Control 11.5. Register Definitions: Nonvolatile Memory 11.5.1. NVMCON0 11.5.2. NVMCON1 11.5.3. NVMCON2 11.5.4. NVMDAT 11.5.5. NVMADR 11.5.6. TABLAT 11.5.7. TBLPTR 12. 8x8 Hardware Multiplier 12.1. Introduction 12.2. Operation 12.3. Register Summary - 8x8 Hardware Multiplier 12.4. Register Definitions: 8x8 Hardware Multiplier 12.4.1. PROD 13. (CRC) Cyclic Redundancy Check Module with Memory Scanner 13.1. CRC Module Overview 13.2. CRC Functional Overview 13.3. CRC Polynomial Implementation 13.4. CRC Data Sources 13.4.1. CRC from User Data 13.4.2. CRC from Flash 13.5. CRC Check Value 13.6. CRC Interrupt 13.7. Configuring the CRC 13.8. Program Memory Scan Configuration 13.9. Scanner Interrupt 13.10. Scanning Modes 13.10.1. Burst Mode 13.10.2. Concurrent Mode 13.10.3. Triggered mode 13.10.4. Peek Mode 13.10.5. Interrupt Interaction 13.10.6. WWDT interaction 13.10.7. In-Circuit Debug (ICD) Interaction 13.10.8. Peripheral Module Disable 13.11. Register Summary - CRC 13.12. Register Definitions: CRC and Scanner Control 13.12.1. CRCCON0 13.12.2. CRCCON1 13.12.3. CRCDAT 13.12.4. CRCACC 13.12.5. CRCSHIFT 13.12.6. CRCXOR 13.12.7. SCANCON0 13.12.8. SCANLADR 13.12.9. SCANHADR 13.12.10. SCANTRIG 14. Interrupts 14.1. Midrange Compatibility 14.2. Interrupt Priority 14.3. Interrupt Response 14.4. INTCON Registers 14.5. PIR Registers 14.6. PIE Registers 14.7. IPR Registers 14.8. INTn Pin Interrupts 14.9. TMR0 Interrupt 14.10. Interrupt-on-Change 14.11. Context Saving During Interrupts 14.12. Register Summary - Interrupt Control 14.13. Register Definitions: Interrupt Control 14.13.1. INTCON 14.13.2. PIR0 14.13.3. PIR1 14.13.4. PIR2 14.13.5. PIR3 14.13.6. PIR4 14.13.7. PIR5 14.13.8. PIR6 14.13.9. PIR7 14.13.10. PIE0 14.13.11. PIE1 14.13.12. PIE2 14.13.13. PIE3 14.13.14. PIE4 14.13.15. PIE5 14.13.16. PIE6 14.13.17. PIE7 14.13.18. IPR0 14.13.19. IPR1 14.13.20. IPR2 14.13.21. IPR3 14.13.22. IPR4 14.13.23. IPR5 14.13.24. IPR6 14.13.25. IPR7 15. I/O Ports 15.1. I/O Priorities 15.2. PORTx Registers 15.2.1. Data Register 15.2.2. Direction Control 15.2.3. Analog Control 15.2.4. Open-Drain Control 15.2.5. Slew Rate Control 15.2.6. Input Threshold Control 15.2.7. Weak Pull-up Control 15.2.8. Edge Selectable Interrupt-on-Change 15.3. PORTE Registers 15.3.1. PORTE on 40/44-Pin Devices 15.3.2. PORTE on 28-Pin Devices 15.3.3. RE3 Weak Pull-Up 15.3.4. PORTE Interrupt-on-Change 15.4. Register Summary - Input/Output 15.5. Register Definitions: Port Control 15.5.1. PORTA 15.5.2. PORTB 15.5.3. PORTC 15.5.4. PORTD 15.5.5. PORTE 15.5.6. TRISA 15.5.7. TRISB 15.5.8. TRISC 15.5.9. TRISD 15.5.10. TRISE 15.5.11. LATA 15.5.12. LATB 15.5.13. LATC 15.5.14. LATD 15.5.15. LATE 15.5.16. ANSELA 15.5.17. ANSELB 15.5.18. ANSELC 15.5.19. ANSELD 15.5.20. ANSELE 15.5.21. WPUA 15.5.22. WPUB 15.5.23. WPUC 15.5.24. WPUD 15.5.25. WPUE 15.5.26. ODCONA 15.5.27. ODCONB 15.5.28. ODCONC 15.5.29. ODCOND 15.5.30. ODCONE 15.5.31. SLRCONA 15.5.32. SLRCONB 15.5.33. SLRCONC 15.5.34. SLRCOND 15.5.35. SLRCONE 15.5.36. INLVLA 15.5.37. INLVLB 15.5.38. INLVLC 15.5.39. INLVLD 15.5.40. INLVLE 16. Interrupt-on-Change 16.1. Features 16.2. Overview 16.3. Block Diagram 16.4. Enabling the Module 16.5. Individual Pin Configuration 16.6. Interrupt Flags 16.7. Clearing Interrupt Flags 16.8. Operation in Sleep 16.9. Register Summary - Interrupt-on-Change 16.10. Register Definitions: Interrupt-on-Change Control 16.10.1. IOCAF 16.10.2. IOCBF 16.10.3. IOCCF 16.10.4. IOCEF 16.10.5. IOCAN 16.10.6. IOCBN 16.10.7. IOCCN 16.10.8. IOCEN 16.10.9. IOCAP 16.10.10. IOCBP 16.10.11. IOCCP 16.10.12. IOCEP 17. (PPS) Peripheral Pin Select Module 17.1. PPS Inputs 17.2. PPS Outputs 17.3. Bidirectional Pins 17.4. PPS Lock 17.5. PPS One-Way Lock 17.6. Operation During Sleep 17.7. Effects of a Reset 17.8. Register Summary - PPS 17.9. Register Definitions: PPS Input and Output Selection 17.9.1. Peripheral xxx Input Selection 17.9.2. Pin Rxy Output Source Selection Register 17.9.3. PPS Lock Register 18. Timer0 Module 18.1. Timer0 Operation 18.1.1. 8-bit Mode 18.1.2. 16-Bit Mode 18.2. Clock Selection 18.2.1. Clock Source Selection 18.2.2. Synchronous Mode 18.2.3. Asynchronous Mode 18.2.4. Programmable Prescaler 18.3. Timer0 Output and Interrupt 18.3.1. Programmable Postscaler 18.3.2. Timer0 Output 18.3.3. Timer0 Interrupt 18.3.4. Timer0 Example 18.4. Operation During Sleep 18.5. Register Summary - Timer0 18.6. Register Definitions: Timer0 Control 18.6.1. T0CON0 18.6.2. T0CON1 18.6.3. TMR0H 18.6.4. TMR0L 19. Timer1 Module with Gate Control 19.1. Timer1 Operation 19.2. Clock Source Selection 19.2.1. Internal Clock Source 19.2.2. External Clock Source 19.3. Timer1 Prescaler 19.4. Secondary Oscillator 19.5. Timer1 Operation in Asynchronous Counter Mode 19.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 19.6. Timer1 16-Bit Read/Write Mode 19.7. Timer1 Gate 19.7.1. Timer1 Gate Enable 19.7.2. Timer1 Gate Source Selection 19.7.3. Timer1 Gate Toggle Mode 19.7.4. Timer1 Gate Single Pulse Mode 19.7.5. Timer1 Gate Value Status 19.7.6. Timer1 Gate Event Interrupt 19.8. Timer1 Interrupt 19.9. Timer1 Operation During Sleep 19.10. CCP Capture/Compare Time Base 19.11. CCP Special Event Trigger 19.12. Peripheral Module Disable 19.13. Register Summary - Timer1 19.14. Register Definitions: Timer1 19.14.1. TxCON 19.14.2. TxGCON 19.14.3. TMRxCLK 19.14.4. TMRxGATE 19.14.5. TMRx 20. Timer2 Module 20.1. Timer2 Operation 20.1.1. Free-Running Period Mode 20.1.2. One-Shot Mode 20.1.3. Monostable Mode 20.2. Timer2 Output 20.3. External Reset Sources 20.4. Timer2 Interrupt 20.5. Operating Modes 20.6. Operation Examples 20.6.1. Software Gate Mode 20.6.2. Hardware Gate Mode 20.6.3. Edge-Triggered Hardware Limit Mode 20.6.4. Level-Triggered Hardware Limit Mode 20.6.5. Software Start One-Shot Mode 20.6.6. Edge-Triggered One-Shot Mode 20.6.7. Edge-Triggered Hardware Limit One-Shot Mode 20.6.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 20.6.9. Edge-Triggered Monostable Modes 20.6.10. Level-Triggered Hardware Limit One-Shot Modes 20.7. Timer2 Operation During Sleep 20.8. Register Summary - Timer2 20.9. Register Definitions: Timer2 Control 20.9.1. TxTMR 20.9.2. TxPR 20.9.3. TxCON 20.9.4. TxHLT 20.9.5. TxCLKCON 20.9.6. TxRST 21. Capture/Compare/PWM Module 21.1. CCP Module Configuration 21.1.1. CCP Modules and Timer Resources 21.1.2. Open-Drain Output Option 21.2. Capture Mode 21.2.1. Capture Sources 21.2.2. Timer1 Mode Resource 21.2.3. Software Interrupt Mode 21.2.4. CCP Prescaler 21.2.5. Capture During Sleep 21.3. Compare Mode 21.3.1. CCPx Pin Configuration 21.3.2. Timer1 Mode Resource 21.3.3. Auto-Conversion Trigger 21.3.4. Compare During Sleep 21.4. PWM Overview 21.4.1. Standard PWM Operation 21.4.2. Setup for PWM Operation 21.4.3. Timer2 Timer Resource 21.4.4. PWM Period 21.4.5. PWM Duty Cycle 21.4.6. PWM Resolution 21.4.7. Operation in Sleep Mode 21.4.8. Changes in System Clock Frequency 21.4.9. Effects of Reset 21.5. Register Summary - CCP Control 21.6. Register Definitions: CCP Control 21.6.1. CCPxCON 21.6.2. CCPxCAP 21.6.3. CCPRx 21.6.4. CCPTMRS 22. (PWM) Pulse-Width Modulation 22.1. Fundamental Operation 22.2. PWM Output Polarity 22.3. PWM Period 22.4. PWM Duty Cycle 22.5. PWM Resolution 22.6. Operation in Sleep Mode 22.7. Changes in System Clock Frequency 22.8. Effects of Reset 22.9. Setup for PWM Operation using PWMx Output Pins 22.9.1. PWMx Pin Configuration 22.10. Setup for PWM Operation to Other Device Peripherals 22.11. Register Summary - Registers Associated with PWM 22.12. Register Definitions: PWM Control 22.12.1. PWMxCON 22.12.2. CCPTMRS 22.12.3. PWMxDC 23. ZCD - Zero-Cross Detection Module 23.1. External Resistor Selection 23.2. ZCD Logic Output 23.3. ZCD Logic Polarity 23.4. ZCD Interrupts 23.5. Correction for ZCPINV Offset 23.5.1. Correction by AC Coupling 23.5.2. Correction By Offset Current 23.6. Handling VPEAK Variations 23.7. Operation During Sleep 23.8. Effects of a Reset 23.9. Disabling the ZCD Module 23.10. Register Summary: ZCD Control 23.11. Register Definitions: ZCD Control 23.11.1. ZCDCON 24. (CWG) Complementary Waveform Generator Module 24.1. Fundamental Operation 24.2. Operating Modes 24.2.1. Half-Bridge Mode 24.2.2. Push-Pull Mode 24.2.3. Full-Bridge Modes 24.2.3.1. Direction Change in Full-Bridge Mode 24.2.3.2. Dead-Band Delay in Full-Bridge Mode 24.2.4. Steering Modes 24.2.4.1. Synchronous Steering Mode 24.2.4.2. Asynchronous Steering Mode 24.3. Start-up Considerations 24.4. Clock Source 24.5. Selectable Input Sources 24.6. Output Control 24.6.1. CWG Outputs 24.6.2. Polarity Control 24.7. Dead-Band Control 24.7.1. Dead-Band Functionality in Half-Bridge mode 24.7.2. Dead-Band Functionality in Full-Bridge mode 24.8. Rising Edge and Reverse Dead Band 24.9. Falling Edge and Forward Dead Band 24.10. Dead-Band Jitter 24.11. Auto-Shutdown 24.11.1. Shutdown 24.11.1.1. Software Generated Shutdown 24.11.1.2. External Input Source 24.11.1.3. Pin Override Levels 24.11.1.4. Auto-Shutdown Interrupts 24.11.2. Auto-Shutdown Restart 24.11.2.1. Software-Controlled Restart 24.11.2.2. Auto-Restart 24.12. Operation During Sleep 24.13. Configuring the CWG 24.14. Register Summary - CWG Control 24.15. Register Definitions: CWG Control 24.15.1. CWGxCON0 24.15.2. CWGxCON1 24.15.3. CWGxCLK 24.15.4. CWGxISM 24.15.5. CWGxSTR 24.15.6. CWGxAS0 24.15.7. CWGxAS1 24.15.8. CWGxDBR 24.15.9. CWGxDBF 25. (CLC) Configurable Logic Cell 25.1. CLC Setup 25.1.1. Data Selection 25.1.2. Data Gating 25.1.3. Logic Function 25.1.4. Output Polarity 25.2. CLC Interrupts 25.3. Output Mirror Copies 25.4. Effects of a Reset 25.5. Operation During Sleep 25.6. CLC Setup Steps 25.7. Register Summary - CLC Control 25.8. Register Definitions: Configurable Logic Cell 25.8.1. CLCxCON 25.8.2. CLCxPOL 25.8.3. CLCxSEL0 25.8.4. CLCxSEL1 25.8.5. CLCxSEL2 25.8.6. CLCxSEL3 25.8.7. CLCxGLS0 25.8.8. CLCxGLS1 25.8.9. CLCxGLS2 25.8.10. CLCxGLS3 25.8.11. CLCDATA 26. (DSM) Data Signal Modulator Module 26.1. DSM Operation 26.2. Modulator Signal Sources 26.3. Carrier Signal Sources 26.4. Carrier Synchronization 26.5. Carrier Source Polarity Select 26.6. Programmable Modulator Data 26.7. Modulated Output Polarity 26.8. Operation in Sleep Mode 26.9. Effects of a Reset 26.10. Peripheral Module Disable 26.11. Register Summary - DSM 26.12. Register Definitions: Modulation Control 26.12.1. MDCON0 26.12.2. MDCON1 26.12.3. MDCARH 26.12.4. MDCARL 26.12.5. MDSRC 27. MSSP - Master Synchronous Serial Port Module 27.1. SPI Mode Overview 27.1.1. SPI Mode Registers 27.2. SPI Mode Operation 27.2.1. SPI Master Mode 27.2.2. SPI Slave Mode 27.2.3. Daisy-Chain Configuration 27.2.4. Slave Select Synchronization 27.2.5. SPI Operation in Sleep Mode 27.3. I2C Mode Overview 27.3.1. Register Definitions: I2C Mode 27.4. I2C Mode Operation 27.4.1. Clock Stretching 27.4.2. Arbitration 27.4.3. Byte Format 27.4.4. Definition of I2C Terminology 27.4.5. SDA and SCL Pins 27.4.6. SDA Hold Time 27.4.7. Start Condition 27.4.8. Stop Condition 27.4.9. Restart Condition 27.4.10. Start/Stop Condition Interrupt Masking 27.4.11. Acknowledge Sequence 27.5. I2C Slave Mode Operation 27.5.1. Slave Mode Addresses 27.5.1.1. I2C Slave 7-bit Addressing Mode 27.5.1.2. I2C Slave 10-bit Addressing Mode 27.5.2. Slave Reception 27.5.2.1. 7-bit Addressing Reception 27.5.2.2. 7-bit Reception with AHEN and DHEN 27.5.3. Slave Transmission 27.5.3.1. Slave Mode Bus Collision 27.5.3.2. 7-bit Transmission 27.5.3.3. 7-bit Transmission with Address Hold Enabled 27.5.4. Slave Mode 10-bit Address Reception 27.5.5. 10-bit Addressing with Address or Data Hold 27.5.6. Clock Stretching 27.5.6.1. Normal Clock Stretching 27.5.6.2. 10-bit Addressing Mode 27.5.6.3. Byte NACKing 27.5.7. Clock Synchronization and the CKP bit 27.5.8. General Call Address Support 27.5.9. SSP Mask Register 27.6. I2C Master Mode 27.6.1. I2C Master Mode Operation 27.6.2. Clock Arbitration 27.6.3. WCOL Status Flag 27.6.4. I2C Master Mode Start Condition Timing 27.6.5. I2C Master Mode Repeated Start Condition Timing 27.6.6. I2C Master Mode Transmission 27.6.6.1. BF Status Flag 27.6.6.2. WCOL Status Flag 27.6.6.3. ACKSTAT Status Flag 27.6.6.4. Typical transmit sequence: 27.6.7. I2C Master Mode Reception 27.6.7.1. BF Status Flag 27.6.7.2. SSPOV Status Flag 27.6.7.3. WCOL Status Flag 27.6.7.4. Typical Receive Sequence: 27.6.8. Acknowledge Sequence Timing 27.6.8.1. Acknowledge Write Collision 27.6.9. Stop Condition Timing 27.6.9.1. Write Collision on Stop 27.6.10. Sleep Operation 27.6.11. Effects of a Reset 27.6.12. Multi-Master Mode 27.6.13. Multi-Master Communication, Bus Collision and Bus Arbitration 27.6.13.1. Bus Collision During a Start Condition 27.6.13.2. Bus Collision During a Repeated Start Condition 27.6.13.3. Bus Collision During a Stop Condition 27.7. Baud Rate Generator 27.8. Register Summary: MSSP Control 27.9. Register Definitions: MSSP Control 27.9.1. SSPxSTAT 27.9.2. SSPxCON1 27.9.3. SSPxCON2 27.9.4. SSPxCON3 27.9.5. SSPxBUF 27.9.6. SSPxADD 27.9.7. SSPxMSK 28. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter 28.1. EUSART Asynchronous Mode 28.1.1. EUSART Asynchronous Transmitter 28.1.1.1. Enabling the Transmitter 28.1.1.2. Transmitting Data 28.1.1.3. Transmit Data Polarity 28.1.1.4. Transmit Interrupt Flag 28.1.1.5. TSR Status 28.1.1.6. Transmitting 9-Bit Characters 28.1.1.7. Asynchronous Transmission Setup 28.1.2. EUSART Asynchronous Receiver 28.1.2.1. Enabling the Receiver 28.1.2.2. Receiving Data 28.1.2.3. Receive Interrupts 28.1.2.4. Receive Framing Error 28.1.2.5. Receive Overrun Error 28.1.2.6. Receiving 9-Bit Characters 28.1.2.7. Address Detection 28.1.2.8. Asynchronous Reception Setup 28.1.2.9. 9-Bit Address Detection Mode Setup 28.1.3. Clock Accuracy with Asynchronous Operation 28.2. EUSART Baud Rate Generator (BRG) 28.2.1. Auto-Baud Detect 28.2.2. Auto-Baud Overflow 28.2.3. Auto-Wake-up on Break 28.2.3.1. Special Considerations 28.2.4. Break Character Sequence 28.2.4.1. Break and Sync Transmit Sequence 28.2.5. Receiving a Break Character 28.3. EUSART Synchronous Mode 28.3.1. Synchronous Master Mode 28.3.1.1. Master Clock 28.3.1.2. Clock Polarity 28.3.1.3. Synchronous Master Transmission 28.3.1.4. Synchronous Master Transmission Setup 28.3.1.5. Synchronous Master Reception 28.3.1.6. Receive Overrun Error 28.3.1.7. Receiving 9-Bit Characters 28.3.1.8. Synchronous Master Reception Setup 28.3.2. Synchronous Slave Mode 28.3.2.1. Slave Clock 28.3.2.2. EUSART Synchronous Slave Transmit 28.3.2.3. Synchronous Slave Transmission Setup 28.3.2.4. EUSART Synchronous Slave Reception 28.3.2.5. Synchronous Slave Reception Setup: 28.4. EUSART Operation During Sleep 28.4.1. Synchronous Receive During Sleep 28.4.2. Synchronous Transmit During Sleep 28.5. Register Summary - EUSART 28.6. Register Definitions: EUSART Control 28.6.1. RCxSTA 28.6.2. TXxSTA 28.6.3. BAUDxCON 28.6.4. SPxBRG 28.6.5. RCxREG 28.6.6. TXxREG 29. (FVR) Fixed Voltage Reference 29.1. Independent Gain Amplifiers 29.2. FVR Stabilization Period 29.3. Register Summary - FVR 29.4. Register Definitions: FVR Control 29.4.1. FVRCON 30. Temperature Indicator Module 30.1. Circuit Operation 30.2. Minimum Operating VDD 30.3. Temperature Output 30.4. ADC Acquisition Time 31. (DAC) 5-Bit Digital-to-Analog Converter Module 31.1. Output Voltage Selection 31.2. Ratiometric Output Level 31.3. DAC Voltage Reference Output 31.4. Operation During Sleep 31.5. Effects of a Reset 31.6. Register Summary - DAC Control 31.7. Register Definitions: DAC Control 31.7.1. DAC1CON0 31.7.2. DAC1CON1 32. (ADC2) Analog-to-Digital Converter with Computation Module 32.1. ADC Configuration 32.1.1. Port Configuration 32.1.2. Channel Selection 32.1.3. ADC Voltage Reference 32.1.4. Conversion Clock 32.1.5. Interrupts 32.1.6. Result Formatting 32.2. ADC Operation 32.2.1. Starting a Conversion 32.2.2. Completion of a Conversion 32.2.3. Terminating a Conversion 32.2.4. ADC Operation During Sleep 32.2.5. External Trigger During Sleep 32.2.6. Auto-Conversion Trigger 32.2.7. ADC Conversion Procedure (Basic Mode) 32.3. ADC Acquisition Requirements 32.4. Capacitive Voltage Divider (CVD) Features 32.4.1. CVD Operation 32.4.2. Precharge Control 32.4.3. Acquisition Control for CVD (ADPRE > 0) 32.4.4. Guard Ring Outputs 32.4.5. Additional Sample-and-Hold Capacitance 32.5. Computation Operation 32.5.1. Digital Filter/Average 32.5.2. Basic Mode 32.5.3. Accumulate Mode 32.5.4. Average Mode 32.5.5. Burst Average Mode 32.5.6. Low-pass Filter Mode 32.5.7. Threshold Comparison 32.5.8. Continuous Sampling Mode 32.5.9. Double Sample Conversion 32.6. Register Summary - ADC Control 32.7. Register Definitions: ADC Control 32.7.1. ADCON0 32.7.2. ADCON1 32.7.3. ADCON2 32.7.4. ADCON3 32.7.5. ADSTAT 32.7.6. ADCLK 32.7.7. ADREF 32.7.8. ADPCH 32.7.9. ADPRE 32.7.10. ADACQ 32.7.11. ADCAP 32.7.12. ADRPT 32.7.13. ADCNT 32.7.14. ADFLTR 32.7.15. ADRES 32.7.16. ADPREV 32.7.17. ADACC 32.7.18. ADSTPT 32.7.19. ADERR 32.7.20. ADLTH 32.7.21. ADUTH 32.7.22. ADACT 33. CMP - Comparator Module 33.1. Comparator Overview 33.2. Comparator Control 33.2.1. Comparator Enable 33.2.2. Comparator Output 33.2.3. Comparator Output Polarity 33.3. Comparator Hysteresis 33.4. Operation With Timer1 Gate 33.4.1. Comparator Output Synchronization 33.5. Comparator Interrupt 33.6. Comparator Positive Input Selection 33.7. Comparator Negative Input Selection 33.8. Comparator Response Time 33.9. Analog Input Connection Considerations 33.10. CWG1 Auto-Shutdown Source 33.11. ADC Auto-Trigger Source 33.12. Even Numbered Timers Reset 33.13. Operation in Sleep Mode 33.14. Register Summary - Comparator 33.15. Register Definitions: Comparator Control 33.15.1. CMxCON0 33.15.2. CMxCON1 33.15.3. CMxNCH 33.15.4. CMxPCH 33.15.5. CMOUT 34. (HLVD) High/Low-Voltage Detect 34.1. Operation 34.2. Setup 34.3. Current Consumption 34.4. HLVD Start-up Time 34.5. Applications 34.6. Operation During Sleep 34.7. Operation During Idle and Doze Modes 34.8. Effects of a Reset 34.9. Register Summary - HLVD 34.10. Register Definitions: HLVD Control 34.10.1. HLVDCON0 34.10.2. HLVDCON1 35. Register Summary 36. In-Circuit Serial Programming™ (ICSP™) 36.1. High-Voltage Programming Entry Mode 36.2. Low-Voltage Programming Entry Mode 36.3. Common Programming Interfaces 37. Instruction Set Summary 37.1. Standard Instruction Set 37.1.1. Standard Instruction Set
 37.2. Extended Instruction Set 37.2.1. Extended Instruction Syntax 37.2.2. Extended Instruction Set 37.2.3. Byte-Oriented and 
Bit-Oriented Instructions in Indexed Literal Offset Mode 37.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 37.2.4. Considerations when Enabling the Extended Instruction Set 37.2.5. Special Considerations with Microchip MPLAB® IDE Tools 38. Development Support 38.1. MPLAB X Integrated Development Environment Software 38.2. MPLAB XC Compilers 38.3. MPASM Assembler 38.4. MPLINK Object Linker/MPLIB Object Librarian 38.5. MPLAB Assembler, Linker and Librarian for Various Device Families 38.6. MPLAB X SIM Software Simulator 38.7. MPLAB REAL ICE In-Circuit Emulator System 38.8. MPLAB ICD 3 In-Circuit Debugger System 38.9. PICkit 3 In-Circuit Debugger/Programmer 38.10. MPLAB PM3 Device Programmer 38.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 38.12. Third-Party Development Tools 39. Electrical Specifications 39.1. Absolute Maximum Ratings(†) 39.2. Standard Operating Conditions 39.3. DC Characteristics 39.3.1. Supply Voltage 39.3.2. Supply Current (IDD)(1,2,4) 39.3.3. Power-Down Current (IPD)(1,2) 39.3.4. I/O Ports 39.3.5. Memory Programming Specifications 39.3.6. Thermal Characteristics 39.4. AC Characteristics 39.4.1. External Clock/Oscillator Timing Requirements 39.4.2. Internal Oscillator Parameters(1) 39.4.3. PLL Specifications 39.4.4. I/O and CLKOUT Timing Specifications 39.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 39.4.6. High/Low-Voltage Detect Characteristics 39.4.7. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 39.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 39.4.9. Comparator Specifications 39.4.10. 5-Bit DAC Specifications 39.4.11. Fixed Voltage Reference (FVR) Specifications 39.4.12. Zero-Cross Detect (ZCD) Specifications 39.4.13. Timer0 and Timer1 External Clock Requirements 39.4.14. Capture/Compare/PWM Requirements (CCP) 39.4.15. EUSART Synchronous Transmission Requirements 39.4.16. EUSART Synchronous Receive Requirements 39.4.17. SPI Mode Requirements 39.4.18. I2C Bus Start/Stop Bits Requirements 39.4.19. I2C Bus Data Requirements 39.4.20. Configurable Logic Cell (CLC) Characteristics 40. DC and AC Characteristics Graphs and Tables 40.1. Analog-to-Digital Converter Oscillator Graphs 40.2. Analog-to-Digital Converter (10-bit) Graphs 40.3. Bandgap Ready Graphs 40.4. Brown-Out Reset Graphs 40.5. Comparator Graphs 40.6. Fixed Voltage Reference Graphs 40.7. I/O Rise/Fall Times Graphs 40.8. IDD Graphs 40.9. Input Buffer Graphs 40.10. IPD Graphs 40.11. HFINTOSC Wake From Sleep Graphs 40.12. LFINTOSC Wake From Sleep Graphs 40.13. Low-Power Brown-Out Reset Graphs 40.14. Low-Voltage Detect Graphs 40.15. OSCTUNE Graphs 40.16. Power-On Reset Graphs 40.17. Power-Up Timer Graphs 40.18. Temperature Indicator Graphs 40.19. VOH - VOL Graphs 40.20. Watchdog Timer Graphs 40.21. Weak Pull-Up Graphs 40.22. Zero-Cross Detection Graphs 41. Packaging Information 41.1. Package Details 42. Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service