Datasheet DF2B5M4ASL (Toshiba) - 2

DF2B5M4ASL 5. Example of Circuit Diagram 6. Quick Reference Data Characteristics Symbol Note Test Condition Min Typ. Max Unit Working peak reverse voltage VRWM (Note 1)    3.6 V Total capacitance Ct VR = 0 V, f = 1 MHz  0.15 0.2 pF Dynamic resistance RDYN (Note 2)   0.7  Ω Electrostatic discharge voltage VESD (Note 3)    16 kV (IEC61000-4-2) (Contact) Note 1: Recommended operating condition. Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A. Note 3: Criterion: No damage to devices. ©2019 2 2019-08-05 Toshiba Electronic Devices & Storage Corporation Rev.1.0