Datasheet PIC16F18324, PIC16F18344, PIC16LF18324, PIC16LF18344 (Microchip)

PIC16(L)F18324/18344 Full-Featured, Low Pin Count Microcontrollers with XLP Description
PIC16(L)F18324/18344 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP, PWM and communications) to add flexibility to the application design.
Core Features Power-Saving Functionality
• C Compiler Optimized RISC Architecture • IDLE mode: ability to put the CPU core to Sleep • Only 48 Instructions while internal peripherals continue operating from • Operating Speed: the system clock - DC – 32 MHz clock input • DOZE mode: ability to run the CPU core slower - 125 ns minimum instruction cycle than the system clock used by the internal periph- • Interrupt Capability erals • 16-Level Deep Hardware Stack • SLEEP mode: Lowest Power Consumption • Up to Four 8-bit Timers • Peripheral Module Disable (PMD): peripheral • Up to Three 16-bit Timers power disable hardware module to minimize • Low-Current Power-on Reset (POR) power consumption of unused peripherals • Power-up Timer (PWRT) • Brown-out Reset (BOR)
Digital Peripherals
• Low-Power BOR (LPBOR) Option • Configurable Logic Cell (CLC): • Extended Watchdog Timer (WDT) with Dedicated - Four CLCs On-Chip Oscillator for Reliable Operation - Integrated combinational and sequential logic • Programmable Code Protection • Complementary Waveform Generator (CWG):
Memory
- Two CWGs - Rising and falling edge dead-band control • 7 Kbytes Program Flash Memory - Full-bridge, half-bridge, 1-channel drive • 512B Data SRAM Memory - Multiple signal sources • 256B of EEPROM • Capture/Compare/PWM (CCP) modules: • Direct, Indirect and Relative Addressing Modes - Four CCPs - 16-bit resolution for Capture/Compare modes
Operating Characteristics
- 10-bit resolution for PWM mode • Operating Voltage Range: • Pulse-Width Modulators (PWM) - 1.8V to 3.6V (PIC16LF18324/18344) - Two 10-bit PWMs - 2.3V to 5.5V (PIC16F18324/18344) • Numerically Controlled Oscillator (NCO): • Temperature Range: - Precision linear frequency generator (@50% - Industrial: -40°C to 85°C duty cycle) with 0.0001% step size of source - Extended: -40°C to 125°C input clock - Input Clock: 0 Hz < FNCO < 32 MHz
eXtreme Low-Power (XLP) Features
- Resolution: FNCO/220 • Serial Communications: • Sleep mode: 40 nA @ 1.8V, typical - EUSART • Watchdog Timer: 250 nA @ 1.8V, typical - RS-232, RS-485, LIN compatible • Secondary Oscillator: 300 nA @ 32 kHz - Auto-Baud Detect, auto-wake-up on start • Operating Current: - Master Synchronous Serial Port (MSSP) - 8 A @ 32 kHz, 1.8V, typical - SPI - 37 A/MHz @ 1.8V, typical - I2C, SMBus, PMBus™ compatible • Data Signal Modulator (DSM): - Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms  2015-2018 Microchip Technology Inc. DS40001800D-page 1 Document Outline Description Core Features Memory Operating Characteristics eXtreme Low-Power (XLP) Features Power-Saving Functionality Digital Peripherals Analog Peripherals Flexible Oscillator Structure PIC16(L)F183XX Family Types Pin Diagrams Pin Allocation Tables Table of Contents Most Current Data Sheet Errata Customer Notification System Full-Featured, Low Pin Count Microcontrollers with XLP 1.0 Device Overview TABLE 1-1: Device Peripheral Summary FIGURE 1-1: PIC16(L)F18324/18344 Block Diagram TABLE 1-2: PIC16(L)F18324 Pinout Description TABLE 1-3: PIC16(L)F18344 Pinout Description 2.0 Guidelines for Getting Started With PIC16(L)F183XX Microcontrollers 2.1 Basic Connection Requirements FIGURE 2-1: Recommended Minimum Connections 2.2 Power Supply Pins 2.2.1 Decoupling Capacitors 2.2.2 Tank Capacitors 2.3 Master Clear (MCLR) Pin 2.4 ICSP™ Pins 2.5 External Oscillator Pins 2.6 Unused I/Os FIGURE 2-2: Suggested Placement of the Oscillator Circuit 3.0 Enhanced Mid-Range CPU FIGURE 3-1: Core Data Path Block Diagram 3.1 Automatic Interrupt Context Saving 3.2 16-Level Stack with Overflow and Underflow 3.3 File Select Registers 3.4 Instruction Set 4.0 Memory Organization 4.1 Program Memory Organization TABLE 4-1: Device Sizes and Addresses FIGURE 4-1: Program Memory Map and Stack for PIC16(L)F18324/18344 4.1.1 Reading Program Memory as Data 4.1.1.1 RETLW Instruction EXAMPLE 4-1: RETLW Instruction 4.1.1.2 Indirect Read with FSR EXAMPLE 4-2: Accessing Program Memory Via FSR 4.1.1.3 NVMREG Access 4.2 Data Memory Organization 4.2.1 Bank Selection FIGURE 4-2: Banked Memory Partitioning 4.2.2 Core Registers TABLE 4-2: Core Registers 4.2.2.1 STATUS Register Register 4-1: STATUS: STATUS Register 4.2.3 Special Function Registers 4.2.4 General Purpose RAM 4.2.5 Common RAM 4.2.6 Device Memory Maps TABLE 4-3: Special Function Register Summary Banks 0-31 (All Banks)(1) TABLE 4-4: Special Function Register Summary Banks 0-31 4.3 PCL and PCLATH FIGURE 4-3: Loading of PC in Different Situations 4.3.1 Modifying PCL 4.3.2 Computed GOTO 4.3.3 Computed Function Calls 4.3.4 Branching 4.4 Stack 4.4.1 Accessing the Stack FIGURE 4-4: Accessing the Stack Example 1 FIGURE 4-5: Accessing the Stack Example 2 FIGURE 4-6: Accessing the Stack Example 3 FIGURE 4-7: Accessing the Stack Example 4 4.5 Indirect Addressing 4.5.1 Traditional/Banked Data Memory FIGURE 4-8: Indirect Addressing FIGURE 4-9: Traditional/Banked Data Memory Map 4.5.2 Linear Data Memory FIGURE 4-10: Linear Data Memory Map 4.5.3 Program Flash Memory FIGURE 4-11: Program Flash Memory Map 4.5.4 Data EEPROM Memory 5.0 Device Configuration 5.1 Configuration Words 5.2 Register Definitions: Configuration Words Register 5-1: Configuration Word 1: Oscillators Register 5-2: Configuration Word 2: Supervisors Register 5-3: Configuration Word 3: Memory Register 5-4: Configuration Word 4: Code Protection 5.3 Code Protection 5.3.1 Program Memory Protection 5.3.2 Data Memory Protection 5.4 Write Protection 5.5 User ID 5.6 Device ID and Revision ID 5.7 Register Definitions: Device and Revision Register 5-5: DEVID: Device ID Register Register 5-6: REVID: Revision ID Register 6.0 Resets FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit 6.1 Power-on Reset (POR) 6.2 Brown-out Reset (BOR) TABLE 6-1: BOR Operating Modes 6.2.1 BOR is Always On 6.2.2 BOR is Off in Sleep 6.2.3 BOR Controlled by Software FIGURE 6-2: Brown-out Situations 6.2.4 BOR Always Off 6.3 Low-Power Brown-out Reset (LPBOR)(PIC16LF18324/18344 Devices Only) 6.3.1 Enabling LPBOR 6.3.1.1 LPBOR Module Output 6.4 MCLR TABLE 6-2: MCLR Configuration 6.4.1 MCLR Enabled 6.4.2 MCLR Disabled 6.5 Watchdog Timer (WDT) Reset 6.6 RESET Instruction 6.7 Stack Overflow/Underflow Reset 6.8 Programming Mode Exit 6.9 Power-up Timer 6.10 Start-up Sequence FIGURE 6-3: Reset Start-up Sequence 6.11 Determining the Cause of a Reset TABLE 6-3: Reset Status Bits and Their Significance TABLE 6-4: Reset Condition for Special Registers Register 6-1: BORCON: Brown-out Reset Control Register 6.12 Power Control (PCON0) Register 6.13 Register Definitions: Power Control Register 6-2: PCON0: Power Control Register 0 TABLE 6-5: Summary of Registers Associated with Resets 7.0 Oscillator Module 7.1 Overview FIGURE 7-1: Simplified PIC® MCU Clock Source Block Diagram 7.2 Clock Source Types 7.2.1 External Clock Sources 7.2.1.1 EC Mode FIGURE 7-2: External Clock (EC) Mode Operation 7.2.1.2 LP, XT, HS Modes FIGURE 7-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 7-4: Ceramic Resonator Operation (XT or HS Mode) 7.2.1.3 Oscillator Start-up Timer (OST) 7.2.1.4 4x PLL 7.2.1.5 Secondary Oscillator FIGURE 7-5: Quartz Crystal Operation (Secondary Oscillator) 7.2.2 Internal Clock Sources 7.2.2.1 HFINTOSC 7.2.2.2 2x PLL 7.2.2.3 Internal Oscillator Frequency Adjustment 7.2.2.4 LFINTOSC 7.2.2.5 Oscillator Status and Manual Enable 7.3 Clock Switching 7.3.1 New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) BITS 7.3.2 PLL Input Switch 7.3.3 Clock Switch and Sleep FIGURE 7-6: Clock Switch (CSWHOLD = 0) FIGURE 7-7: Clock Switch (CSWHOLD = 1) FIGURE 7-8: Clock Switch Abandoned 7.4 Fail-Safe Clock Monitor FIGURE 7-9: FSCM Block Diagram 7.4.1 Fail-Safe Detection 7.4.2 Fail-Safe Operation 7.4.3 Fail-Safe Condition Clearing 7.4.4 Reset or Wake-up from Sleep FIGURE 7-10: FSCM Timing Diagram 7.5 Register Definitions: Oscillator Control Register 7-1: OSCCON1: Oscillator Control Register 1 Register 7-2: OSCCON2: Oscillator Control Register 2 TABLE 7-1: NOSC/COSC Bit Settings TABLE 7-2: NDIV/CDIV Bit Settings Register 7-3: OSCCON3: Oscillator Control Register 3 Register 7-4: OSCSTAT1: Oscillator STATUS Register 1 Register 7-5: OSCEN: Oscillator Manual Enable Register Register 7-6: OSCFRQ: HFINTOSC Frequency Selection Register Register 7-7: OSCTUNE: HFINTOSC Tuning Register TABLE 7-3: Summary of Registers Associated with Clock Sources TABLE 7-4: Summary of Configuration Word with Clock Sources 8.0 Interrupts FIGURE 8-1: Interrupt Logic 8.1 Operation 8.2 Interrupt Latency FIGURE 8-2: Interrupt Latency FIGURE 8-3: INT Pin Interrupt Timing 8.3 Interrupts During Sleep 8.4 INT Pin 8.5 Automatic Context Saving 8.6 Register Definitions: Interrupt Control Register 8-1: INTCON: Interrupt Control Register Register 8-2: PIE0: Peripheral Interrupt Enable Register 0 Register 8-3: PIE1: Peripheral Interrupt Enable Register 1 Register 8-4: PIE2: Peripheral Interrupt Enable Register 2 Register 8-5: PIE3: Peripheral Interrupt Enable Register 3 Register 8-6: PIE4: Peripheral Interrupt Enable Register 4 Register 8-7: PIR0: Peripheral Interrupt Request Register 0 Register 8-8: PIR1: Peripheral Interrupt Request Register 1 Register 8-9: PIR2: Peripheral Interrupt Request Register 2 Register 8-10: PIR3: Peripheral Interrupt Request Register 3 Register 8-11: PIR4: Peripheral Interrupt Request Register 4 TABLE 8-1: Summary of Registers Associated with Interrupts 9.0 Power-Saving Operation Modes 9.1 DOZE Mode 9.1.1 Doze Operation 9.1.2 Interrupts During Doze FIGURE 9-1: Doze Mode Operation Example 9.2 IDLE Mode 9.2.1 IDLE and Interrupts 9.2.2 IDLE and WDT 9.3 Sleep Mode 9.3.1 Wake-up from Sleep 9.3.2 Wake-up Using Interrupts FIGURE 9-2: Wake-up from Sleep through Interrupt 9.3.3 Low-Power Sleep Mode 9.3.3.1 Sleep Current vs. Wake-up Time 9.3.3.2 Peripheral Usage in Sleep 9.4 Register Definitions: Voltage Regulator Control Register 9-1: VREGCON: Voltage Regulator Control Register(1) Register 9-2: CPUDOZE: Doze and Idle Register TABLE 9-1: Summary of Registers Associated with Power-down Mode 10.0 Watchdog Timer (WDT) FIGURE 10-1: Watchdog Timer Block Diagram 10.1 Independent Clock Source 10.2 WDT Operating Modes 10.2.1 WDT is Always On 10.2.2 WDT is Off in Sleep 10.2.3 WDT Controlled By Software 10.2.4 WDT is Always Off TABLE 10-1: WDT Operating Modes 10.3 Time-out Period 10.4 Clearing the WDT 10.5 Operation During Sleep TABLE 10-2: WDT Clearing Conditions 10.6 Register Definitions: Watchdog Control Register 10-1: WDTCON: Watchdog Timer Control Register TABLE 10-3: Summary of Registers Associated with Watchdog Timer TABLE 10-4: Summary of Configuration Word with Watchdog Timer 11.0 Nonvolatile Memory (NVM) Control 11.1 Program Flash Memory TABLE 11-1: Flash Memory Organization by Device 11.1.1 Program Memory Voltages 11.1.1.1 Programming Externally 11.1.1.2 Self-Programming 11.2 Data EEPROM 11.3 FSR and INDF Access 11.3.1 FSR Read 11.3.2 FSR Write 11.4 NVMREG Access 11.4.1 NVMREG Read Operation FIGURE 11-1: Program Flash Memory Read Flowchart EXAMPLE 11-1: Program Flash Memory Read 11.4.2 NVM Unlock Sequence FIGURE 11-2: NVM Unlock Sequence Flowchart EXAMPLE 11-2: NVM Unlock Sequence 11.4.3 NVMREG Write to EEPROM 11.4.4 NVMREG Erase of Program Flash Memory FIGURE 11-3: NVM Erase Flowchart EXAMPLE 11-3: Erasing One Row of Program Flash Memory TABLE 11-2: NVM Organization and Access Information 11.4.5 NVMREG Write to Program Flash Memory FIGURE 11-4: Block Writes to Program Flash Memory with 32 Write Latches FIGURE 11-5: Program Flash Memory Write Flowchart EXAMPLE 11-4: Writing to Program Flash Memory 11.4.6 Modifying Program Flash Memory FIGURE 11-6: Program Flash Memory Modify Flowchart 11.4.7 NVMREG EEPROM, User ID, Device ID and Configuration Word Access TABLE 11-3: EEPROM, User ID, Dev/REV ID and Configuration Word Access (NVMREGS = 1) 11.4.8 Write Verify FIGURE 11-7: Program Flash Memory Verify Flowchart 11.4.9 WRERR Bit TABLE 11-4: Actions for Program Flash Memory when WR = 1 11.5 Register Definitions: Program Flash Memory Control Register 11-1: NVMDATL: Nonvolatile Memory Data Low Byte Register Register 11-2: NVMDATH: Nonvolatile Memory Data High Byte Register Register 11-3: NVMADRL: Nonvolatile Memory Address Low Byte Register Register 11-4: NVMADRH: Nonvolatile Memory Address High Byte Register Register 11-5: NVMCON1: Nonvolatile Memory Control 1 Register Register 11-6: NVMCON2: Nonvolatile Memory Control 2 Register TABLE 11-5: Summary of Registers Associated with Nonvolatile Memory (NVM) TABLE 11-6: Summary of Configuration Word with Nonvolatile Memory (NVM) 12.0 I/O Ports TABLE 12-1: Port Availability per Device FIGURE 12-1: Generic I/O Port Operation 12.1 I/O Priorities 12.2 PORTA Registers 12.2.1 Data Register EXAMPLE 12-1: Initializing PORTA 12.2.2 Direction Control 12.2.3 Open-Drain Control 12.2.4 Slew Rate Control 12.2.5 Input Threshold Control 12.2.6 Analog Control 12.2.7 Weak Pull-up Control 12.2.8 PORTA Functions and Output Priorities 12.3 Register Definitions: PORTA Register 12-1: PORTA: PORTA Register Register 12-2: TRISA: PORTA Tri-State Register Register 12-3: LATA: PORTA Data Latch Register Register 12-4: ANSELA: PORTA Analog Select Register Register 12-5: WPUA: Weak Pull-up PORTA Register Register 12-6: ODCONA: PORTA Open-Drain Control Register Register 12-7: SLRCONA: PORTA Slew Rate Control Register Register 12-8: INLVLA: PORTA Input Level Control Register TABLE 12-2: Summary of Registers Associated with PORTA TABLE 12-3: Summary of Configuration Word with PORTA 12.4 PORTB Registers (PIC16(L)F18344 Only) 12.4.1 Data Register 12.4.2 Direction Control 12.4.3 Input Threshold Control 12.4.4 Open-Drain Control 12.4.5 Slew Rate Control 12.4.6 Analog Control 12.4.7 Weak Pull-up Control 12.4.8 PORTB Functions and Output Priorities 12.5 Register Definitions: PORTB Register 12-9: PORTB: PORTB Register Register 12-10: TRISB: PORTB Tri-State Register Register 12-11: LATB: PORTB Data Latch Register Register 12-12: ANSELB: PORTB Analog Select Register Register 12-13: WPUB: Weak Pull-up PORTB Register Register 12-14: ODCONB: PORTB Open-Drain Control Register Register 12-15: SLRCONB: PORTB Slew Rate Control Register Register 12-16: INLVLB: PORTB Input Level Control Register TABLE 12-4: Summary of Registers Associated with PORTB 12.6 PORTC Registers 12.6.1 Data Register 12.6.2 Direction Control 12.6.3 Input Threshold Control 12.6.4 Open-Drain Control 12.6.5 Slew Rate Control 12.6.6 Analog Control 12.6.7 Weak Pull-up Control 12.6.8 PORTC Functions and Output Priorities 12.7 Register Definitions: PORTC Register 12-17: PORTC: PORTC Register Register 12-18: TRISC: PORTC Tri-State Register Register 12-19: LATC: PORTC Data Latch Register Register 12-20: ANSELC: PORTC Analog Select Register Register 12-21: WPUC: Weak Pull-up PORTC Register Register 12-22: ODCONC: PORTC Open-Drain Control Register Register 12-23: SLRCONC: PORTC Slew Rate Control Register Register 12-24: INLVLC: PORTC Input Level Control Register TABLE 12-5: Summary of Registers Associated with PORTC 13.0 Peripheral Pin Select (PPS) Module 13.1 PPS Inputs 13.2 PPS Outputs FIGURE 13-1: Simplified PPS Block Diagram 13.3 Bidirectional Pins 13.4 PPSLOCKED Bit EXAMPLE 13-1: PPS Lock/Unlock sequence 13.5 PPS1WAY Bit 13.6 Operation During Sleep 13.7 Effects of a Reset 13.8 Register Definitions: PPS Input Selection Register 13-1: xxxPPS: Peripheral xxx Input Selection Register 13-2: RxyPPS: Pin Rxy Output Source Selection Register Register 13-3: PPSLOCK: PPS Lock Register TABLE 13-1: Summary of Registers Associated with the PPS Module 14.0 Peripheral Module Disable 14.1 Disabling a Module 14.2 Enabling a Module 14.3 System Clock Disable Register 14-1: PMD0: PMD Control Register 0 Register 14-2: PMD1: PMD Control Register 1 Register 14-3: PMD2: PMD Control Register 2 Register 14-4: PMD3: PMD Control Register 3 Register 14-5: PMD4: PMD Control Register 4 Register 14-6: PMD5: PMD Control Register 5 15.0 Interrupt-on-Change 15.1 Enabling the Module 15.2 Individual Pin Configuration 15.3 Interrupt Flags 15.3.1 Clearing Interrupt Flags EXAMPLE 15-1: Clearing Interrupt Flags (PORTA Example) 15.4 Operation in Sleep FIGURE 15-1: Interrupt-on-Change Block Diagram (PORTA Example) 15.5 Register Definitions: Interrupt-on-Change Control Register 15-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 15-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 15-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 15-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register(1) Register 15-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register(1) Register 15-6: IOCBF: Interrupt-on-Change PORTB Flag Register(1) Register 15-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 15-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 15-9: IOCCF: Interrupt-on-Change PORTC Flag Register TABLE 15-1: Summary of Registers Associated with Interrupt-on-Change 16.0 Fixed Voltage Reference (FVR) 16.1 Independent Gain Amplifiers 16.2 FVR Stabilization Period FIGURE 16-1: Voltage Reference Block Diagram 16.3 Register Definitions: FVR Control Register 16-1: FVRCON: Fixed Voltage Reference Control Register TABLE 16-1: Summary of Registers Associated with Fixed Voltage Reference 17.0 Temperature Indicator Module 17.1 Circuit Operation EQUATION 17-1: Vout Ranges FIGURE 17-1: Temperature Circuit Diagram 17.2 Minimum Operating Vdd TABLE 17-1: Recommended Vdd vs. Range 17.3 Temperature Output 17.4 ADC Acquisition Time TABLE 17-2: Summary of Registers Associated with the Temperature Indicator 18.0 Comparator Module 18.1 Comparator Overview TABLE 18-1: Available Comparators FIGURE 18-1: Single Comparator FIGURE 18-2: Comparator Module Simplified Block Diagram 18.2 Comparator Control 18.2.1 Comparator Enable 18.2.2 Comparator Output 18.2.3 Comparator Output Polarity TABLE 18-2: Comparator Output State vs. Input Conditions 18.3 Comparator Hysteresis 18.4 Timer1 Gate Operation 18.4.1 Comparator Output Synchronization 18.5 Comparator Interrupt 18.6 Comparator Positive Input Selection 18.7 Comparator Negative Input Selection 18.8 Comparator Response Time 18.9 Analog Input Connection Considerations FIGURE 18-3: Analog Input Model 18.10 CWG Auto-shutdown Source 18.11 Operation in Sleep Mode 18.12 Register Definitions: Comparator Control Register 18-1: CMxCON0: Comparator Cx Control Register 0 Register 18-2: CMxCON1: Comparator Cx Control Register 1 Register 18-3: CMOUT: Comparator Output Register TABLE 18-3: Summary of Registers Associated with Comparator Module 19.0 Pulse-Width Modulation (PWM) FIGURE 19-1: PWM Output 19.1 Standard PWM Mode FIGURE 19-2: Simplified PWM Block Diagram 19.1.1 PWM Period EQUATION 19-1: PWM Period 19.1.2 PWM Duty Cycle EQUATION 19-2: Pulse Width EQUATION 19-3: Duty Cycle Ratio 19.1.3 PWM Resolution EQUATION 19-4: 19.1.4 Operation in Sleep Mode 19.1.5 Changes in System Clock Frequency 19.1.6 Effects of Reset 19.1.7 Setup for PWM Operation 19.2 Register Definitions: PWM Control Register 19-1: PWMxCON: PWM Control Register Register 19-2: PWMXDCH: PWM Duty Cycle High Bits Register 19-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 19-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 19-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) Register 19-4: PWMTMRS: PWM Timers Control Register TABLE 19-3: Summary of Registers Associated with PWMx 20.0 Complementary Waveform Generator (CWG) Module 20.1 Fundamental Operation 20.2 Operating Modes 20.2.1 Half-Bridge Mode FIGURE 20-1: CWGx Half-Bridge Mode Operation 20.2.2 Push-Pull Mode FIGURE 20-2: CWGx Push-Pull Mode Operation 20.2.3 Steering Modes 20.2.3.1 Synchronous Steering Mode FIGURE 20-3: Example of Synchronous Steering (MODE<2:0> = 001) 20.2.3.2 Asynchronous Steering Mode FIGURE 20-4: Example of Asynchronous Steering (MODE<2:0> = 000) 20.2.3.3 Start-up Considerations 20.2.4 Full-Bridge Modes FIGURE 20-5: Example of Full-Bridge Application 20.2.4.1 Full-Bridge Forward Mode 20.2.4.2 Full-Bridge Reverse Mode FIGURE 20-6: Example of Full-Bridge Output 20.2.4.3 Direction Change in Full-Bridge Mode 20.2.4.4 Dead-Band Delay in Full-Bridge Mode FIGURE 20-7: Example of PWM Direction Change at Near 100% Duty Cycle FIGURE 20-8: Simplified CWGx Block Diagram (Half-Bridge Mode, MODE<2:0> = 100) FIGURE 20-9: Simplified CWG Block Diagram (Push-Pull Mode, MODE <2:0> = 101) FIGURE 20-10: Simplified CWG Block Diagram (Output Steering Modes) FIGURE 20-11: Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) 20.3 Clock Source 20.4 Selectable Input Sources TABLE 20-1: Selectable Input Sources 20.5 Output Control 20.5.1 CWGx Outputs 20.5.2 Polarity Control 20.6 Dead-Band Control 20.6.1 Rising Edge and Reverse Dead Band 20.6.2 Falling Edge and Forward Dead Band 20.6.3 Dead-Band Jitter EQUATION 20-1: Dead-Band Delay Time Calculation 20.7 Auto-Shutdown Control 20.7.1 Shutdown 20.7.1.1 Software-Generated Shutdown 20.7.1.2 External Input Source Shutdown 20.7.1.3 Pin Override Levels 20.7.1.4 Auto-Shutdown Interrupts 20.8 Auto-Shutdown Restart 20.8.1 Software-Controlled Restart 20.8.2 Auto-Restart 20.9 Operation During Sleep 20.10 Configuring the CWG 20.11 Register Definitions: CWG Control Register 20-1: CWGxCON0: CWGx Control Register 0 Register 20-2: CWGxCON1: CWGx Control Register 1 Register 20-3: CWGxCLKCON: CWGx Clock Input Selection Register Register 20-4: CWGxDAT: CWGx Data Input Selection Register Register 20-5: CWGxSTR(1): CWG Steering Control Register Register 20-6: CWGxAS0: CWG Auto-Shutdown Control Register 0 Register 20-7: CWGxAS1: CWG Auto-Shutdown Control Register 1 Register 20-8: CWGxDBR: CWGx Rising Dead-Band Count Register Register 20-9: CWGxDBF: CWGx Falling Dead-Band Count Register TABLE 20-2: Summary of Registers Associated with CWGx 21.0 Configurable Logic Cell (CLC) FIGURE 21-1: CLCx Simplified Block Diagram 21.1 CLCx Setup 21.1.1 Data Selection TABLE 21-1: CLCx Data Input Selection 21.1.2 Input Data Selection Gates TABLE 21-2: Data Gating Logic 21.1.3 Logic Function 21.1.4 Output Polarity 21.2 CLCx Interrupts 21.3 Output Mirror Copies 21.4 Effects of a Reset 21.5 Operation During Sleep 21.6 CLCx Setup Steps FIGURE 21-2: Input Data Selection and Gating FIGURE 21-3: Programmable Logic Functions 21.7 Register Definitions: CLC Control Register 21-1: CLCxCON: Configurable Logic Cell Control Register Register 21-2: CLCxPOL: Signal Polarity Control Register Register 21-3: CLCxSEL0: Generic CLCx Data 0 Select Register Register 21-4: CLCxSEL1: Generic CLCx Data 1 Select Register Register 21-5: CLCxSEL2: Generic CLCx Data 2 Select Register Register 21-6: CLCxSEL3: Generic CLCx Data 3 Select Register Register 21-7: CLCxGLS0: Gate 0 Logic Select Register Register 21-8: CLCxGLS1: Gate 1 Logic Select Register Register 21-9: CLCxGLS2: Gate 2 Logic Select Register Register 21-10: CLCxGLS3: Gate 3 Logic Select Register Register 21-11: CLCDATA: CLC Data Output TABLE 21-3: Summary of Registers Associated with CLCx 22.0 Analog-to-Digital Converter (ADC) Module FIGURE 22-1: ADC Block Diagram 22.1 ADC Configuration 22.1.1 Port Configuration 22.1.2 Channel Selection 22.1.3 ADC Voltage Reference 22.1.4 Conversion Clock TABLE 22-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 22-2: Analog-to-Digital Conversion Tad Cycles 22.1.5 Interrupts 22.1.6 Result Formatting FIGURE 22-3: 10-bit ADC Conversion Result Format 22.2 ADC Operation 22.2.1 Starting a Conversion 22.2.2 Completion of a Conversion 22.2.3 Terminating a Conversion 22.2.4 ADC Operation During Sleep 22.2.5 Auto-Conversion Trigger TABLE 22-2: ADC Auto-Conversion Sources 22.2.6 ADC Conversion Procedure EXAMPLE 22-1: ADC Conversion 22.3 ADC Acquisition Requirements EQUATION 22-1: Acquisition Time Example FIGURE 22-4: Analog Input Model FIGURE 22-5: ADC Transfer Function 22.4 Register Definitions: ADC Control Register 22-1: ADCON0: ADC Control Register 0 Register 22-2: ADCON1: ADC Control Register 1 Register 22-3: ADACT: A/D Auto-Conversion Trigger Register 22-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 22-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 22-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 22-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 TABLE 22-3: Summary of Registers Associated with ADC 23.0 Numerically Controlled Oscillator (NCO1) Module FIGURE 23-1: Numerically Controlled Oscillator Module Simplified Block Diagram 23.1 NCO1 Operation EQUATION 23-1: NC01 Overflow Frequency 23.1.1 NCO1 Clock Sources 23.1.2 Accumulator 23.1.3 Adder 23.1.4 Increment Registers 23.2 Fixed Duty Cycle (FDC) Mode EQUATION 23-2: FDC Frequency 23.3 Pulse Frequency (PF) Mode 23.3.1 Output Pulse Width Control 23.4 Output Polarity Control FIGURE 23-2: FDC Output Mode Operation Diagram 23.5 Interrupts 23.6 Effects of a Reset 23.7 Operation in Sleep 23.8 NCO1 Control Registers Register 23-1: NCO1CON: NCO1 Control Register Register 23-2: NCO1CLK: NCO1 Input Clock Control Register Register 23-3: NCO1ACCL: NCO1 Accumulator Register – Low Byte Register 23-4: NCO1ACCH: NCO1 Accumulator Register – High Byte Register 23-5: NCO1ACCU: NCO1 Accumulator Register – Upper Byte(1) Register 23-6: NCO1INCL(1,2): NCO1 Increment Register – Low Byte Register 23-7: NCO1INCH(1): NCO1 Increment Register – High Byte Register 23-8: NCO1INCU(1): NCO1 Increment Register – Upper Byte TABLE 23-1: Summary of Registers Associated with NCO1 24.0 5-bit Digital-to-Analog Converter (DAC1) Module 24.1 Output Voltage Selection EQUATION 24-1: DAC Output Voltage 24.2 Ratiometric Output Level 24.3 DAC Voltage Reference Output FIGURE 24-1: Digital-to-Analog Converter Block Diagram FIGURE 24-2: Voltage Reference Output Buffer Example 24.4 Operation During Sleep 24.5 Effects of a Reset 24.6 Register Definitions: DAC Control Register 24-1: DACCON0: Voltage Reference Control Register 0 Register 24-2: DACCON1: Voltage Reference Control Register 1 TABLE 24-1: Summary of Registers Associated with the DAC1 Module 25.0 Data Signal Modulator (DSM) Module FIGURE 25-1: Simplified Block Diagram of the Data Signal Modulator 25.1 DSM Operation 25.2 Modulator Signal Sources 25.3 Carrier Signal Sources 25.4 Carrier Synchronization FIGURE 25-2: On Off Keying (OOK) Synchronization FIGURE 25-3: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0) FIGURE 25-4: Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0) FIGURE 25-5: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1) FIGURE 25-6: Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1) 25.5 Carrier Source Polarity Select 25.6 Programmable Modulator Data 25.7 Modulated Output Polarity 25.8 Slew Rate Control 25.9 Operation in Sleep Mode 25.10 Effects of a Reset 25.11 Register Definitions: Modulation Control Register 25-1: MDCON: Modulation Control Register Register 25-2: MDSRC: Modulation Source Control Register Register 25-3: MDCARH: Modulation High Carrier Control Register Register 25-4: MDCARL: Modulation Low Carrier Control Register TABLE 25-1: Summary of Registers Associated with Data Signal Modulator Mode 26.0 Timer0 Module 26.1 Timer0 Operation 26.1.1 16-bit Mode 26.1.1.1 Timer0 Reads and Writes in 16-bit Mode 26.1.2 8-bit Mode 26.1.3 Counter Mode 26.1.4 Timer Mode 26.1.5 Asynchronous Mode 26.1.6 Synchronous Mode 26.2 Clock Source Selection 26.2.1 Internal Clock Source 26.2.2 External Clock Source 26.3 Programmable Prescaler 26.4 Programmable Postscaler 26.5 Operation During Sleep 26.6 Timer0 Interrupts 26.7 Timer0 Output FIGURE 26-1: Block Diagram of Timer0 26.8 Register Definitions: Timer0 Register Register 26-1: TMR0L: TIMER0 Count Register Register 26-2: TMR0H: TIMER0 Period Register Register 26-3: T0CON0: TIMER0 Control Register 0 Register 26-4: T0CON1: TIMER0 Control Register 1 TABLE 26-1: Summary of Registers Associated with Timer0 27.0 Timer1/3/5 Module with Gate Control FIGURE 27-1: Timer1 Block Diagram 27.1 Timer1 Operation TABLE 27-1: Timer1 Enable Selections 27.2 Clock Source Selection TABLE 27-2: Clock Source Selections 27.2.1 Timer1 (Secondary) Oscillator 27.3 Timer1 Prescaler 27.4 Timer1 Operation in Asynchronous Mode 27.4.1 Reading and Writing Timer1 in Asynchronous Mode 27.5 Timer1 Gate 27.5.1 Timer1 Gate Enable TABLE 27-3: Timer1 Gate Enable Selections 27.5.2 Timer1 Gate Source Selection TABLE 27-4: Timer1 Gate Sources 27.5.2.1 T1G Pin Gate Operation 27.5.2.2 Timer0 Overflow Gate Operation 27.5.2.3 Comparator C1 Gate Operation 27.5.2.4 Comparator C2 Gate Operation 27.5.3 Timer1 Gate Toggle Mode 27.5.4 Timer1 Gate Single-Pulse Mode 27.5.5 Timer1 Gate Value Status 27.6 Timer1 Interrupt 27.6.1 Timer1 Gate Event Interrupt 27.7 Timer1 Operation During Sleep 27.8 CCP Capture/Compare Time Base 27.9 CCP Auto-Conversion Trigger FIGURE 27-2: Timer1 Incrementing Edge FIGURE 27-3: Timer1 Gate Enable Mode FIGURE 27-4: Timer1 Gate Toggle Mode FIGURE 27-5: Timer1 Gate Single-Pulse Mode FIGURE 27-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 27.10 Register Definitions: Timer1/3/5 Control Register 27-1: TxCON(1): Timerx Control Register Register 27-2: TxGCON(1): Timerx Gate Control Register Register 27-3: TMRxL(1): Timerx Low Byte Register Register 27-4: TMRxH(1): Timerx High Byte Register TABLE 27-5: Summary of Registers Associated with Timer1/3/5 28.0 Timer2/4/6 Module FIGURE 28-1: Timer2/4/6 Block Diagram 28.1 Timer2 Operation 28.2 Timer2 Interrupt 28.3 Timer2 Output 28.4 Timer2 Operation During Sleep 28.5 Register Definitions: Timer2/4/6 Control Register 28-1: TxCON(1): Timerx Control Register Register 28-2: TMRx(1): Timerx Count Register Register 28-3: PRx: Timerx Period Register(1) TABLE 28-1: Summary of Registers Associated with Timer2/4/6 29.0 Capture/Compare/PWM Modules 29.1 CCP/PWM Clock Selection 29.2 Capture Mode 29.2.1 Capture Sources FIGURE 29-1: Capture Mode Operation Block Diagram 29.2.2 Timer1/3/5 Mode Resource 29.2.3 Software Interrupt Mode 29.2.4 CCP Prescaler EXAMPLE 29-1: Changing Between Capture Prescalers 29.2.5 Capture During Sleep 29.3 Compare Mode FIGURE 29-2: Compare Mode Operation Block Diagram 29.3.1 CCPx Pin Configuration 29.3.2 Timer1/3/5 Mode Resource 29.3.3 Auto-Conversion Trigger 29.3.4 Compare During Sleep 29.3.5 Compare Interrupts 29.4 PWM Overview 29.4.1 Standard PWM Operation FIGURE 29-3: CCP PWM Output Signal FIGURE 29-4: Simplified PWM Block Diagram 29.4.2 Setup for PWM Operation 29.4.3 Timer2/4/6 Timer Resource 29.4.4 PWM Period EQUATION 29-1: PWM Period 29.4.5 PWM Duty Cycle FIGURE 29-5: PWM 10-bit Alignment Block Diagram EQUATION 29-2: Pulse Width EQUATION 29-3: Duty Cycle Ratio 29.4.6 PWM Resolution EQUATION 29-4: PWM Resolution TABLE 29-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 29-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 29.4.7 Operation in Sleep Mode 29.4.8 Changes in System Clock Frequency 29.4.9 Effects of Reset 29.5 Register Definitions: CCP Control Register 29-1: CCPXCON: CCPx Control Register Register 29-2: CCPXCAP: Capture Input Selection Register Register 29-3: CCPRXL Register: CCPX Register Low Byte Register 29-4: CCPRXH Register: CCPX Register High Byte Register 29-5: CCPTMRS: CCP Timers Control Register TABLE 29-3: Timer Selections TABLE 29-4: Summary Of Registers Associated with CCPx 30.0 Master Synchronous Serial Port (MSSP1) Module 30.1 MSSP1 Module Overview FIGURE 30-1: MSSP Block Diagram (SPI mode) FIGURE 30-2: MSSP Block Diagram (I2C Master mode) FIGURE 30-3: MSSP Block Diagram (I2C Slave mode) 30.2 SPI Mode Overview FIGURE 30-4: SPI Master and Multiple Slave Connection 30.2.1 SPI Mode Registers 30.2.2 SPI Mode Operation FIGURE 30-5: SPI Master/Slave Connection 30.2.3 SPI Master Mode FIGURE 30-6: SPI Mode Waveform (Master Mode) 30.2.4 SPI Slave Mode 30.2.4.1 Daisy-Chain Configuration 30.2.5 Slave Select Synchronization FIGURE 30-7: SPI Daisy-Chain Connection FIGURE 30-8: Slave Select Synchronous Waveform FIGURE 30-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 30-10: SPI Mode Waveform (Slave Mode with CKE = 1) 30.2.6 SPI Operation in Sleep Mode 30.3 I2C Mode Overview FIGURE 30-11: I2C Master/ Slave Connection 30.3.1 Clock Stretching 30.3.2 Arbitration 30.4 I2C Mode Operation 30.4.1 Byte Format 30.4.2 Definition of I2C Terminology 30.4.3 SDA and SCL Pins 30.4.4 SDA Hold Time TABLE 30-1: I2C Bus terms 30.4.5 Start Condition 30.4.6 Stop Condition 30.4.7 Restart Condition 30.4.8 Start/Stop Condition Interrupt masking FIGURE 30-12: I2C Start and Stop Conditions FIGURE 30-13: I2C Restart Condition 30.4.9 Acknowledge Sequence 30.5 I2C Slave Mode Operation 30.5.1 Slave Mode Addresses 30.5.1.1 I2C Slave 7-bit Addressing Mode 30.5.1.2 I2C Slave 10-bit Addressing Mode 30.5.2 Slave Reception 30.5.2.1 7-bit Addressing Reception 30.5.2.2 7-bit Reception with AHEN and DHEN FIGURE 30-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 30-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 30-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 30-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) 30.5.3 Slave Transmission 30.5.3.1 Slave Mode Bus Collision 30.5.3.2 7-bit Transmission FIGURE 30-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) 30.5.3.3 7-bit Transmission with Address Hold Enabled FIGURE 30-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) 30.5.4 Slave Mode 10-bit Address Reception 30.5.5 10-bit Addressing with Address or Data Hold FIGURE 30-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 30-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 30-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 30.5.6 Clock Stretching 30.5.6.1 Normal Clock Stretching 30.5.6.2 10-bit Addressing Mode 30.5.6.3 Byte NACKing 30.5.7 Clock Synchronization and the CKP Bit FIGURE 30-23: Clock Synchronization Timing 30.5.8 General Call Address Support FIGURE 30-24: Slave Mode General Call Address Sequence 30.5.9 SSP Mask Register 30.6 I2C Master Mode 30.6.1 I2C Master Mode Operation 30.6.2 Clock Arbitration FIGURE 30-25: Baud Rate Generator Timing with Clock Arbitration 30.6.3 WCOL Status Flag 30.6.4 I2C Master Mode Start Condition Timing FIGURE 30-26: First Start Bit Timing 30.6.5 I2C Master Mode Repeated Start Condition Timing FIGURE 30-27: Repeated Start Condition Waveform 30.6.6 I2C Master Mode Transmission 30.6.6.1 BF Status Flag 30.6.6.2 WCOL Status Flag 30.6.6.3 ACKSTAT Status Flag 30.6.6.4 Typical Transmit Sequence FIGURE 30-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) 30.6.7 I2C Master Mode Reception 30.6.7.1 BF Status Flag 30.6.7.2 SSPOV Status Flag 30.6.7.3 WCOL Status Flag 30.6.7.4 Typical Receive Sequence: FIGURE 30-29: I2C Master Mode Waveform (Reception, 7-bit Address) 30.6.8 Acknowledge Sequence Timing 30.6.8.1 WCOL Status Flag 30.6.9 Stop Condition Timing 30.6.9.1 WCOL Status Flag FIGURE 30-30: Acknowledge Sequence Waveform FIGURE 30-31: Stop Condition Receive or Transmit Mode 30.6.10 Sleep Operation 30.6.11 Effects of a Reset 30.6.12 Multi-Master Mode 30.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration FIGURE 30-32: Bus Collision Timing for Transmit and Acknowledge 30.6.13.1 Bus Collision During a Start Condition FIGURE 30-33: Bus Collision During Start Condition (SDA Only) FIGURE 30-34: Bus Collision During Start Condition (SCL = 0) FIGURE 30-35: BRG Reset Due to SDA Arbitration During Start Condition 30.6.13.2 Bus Collision During a Repeated Start Condition FIGURE 30-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 30-37: Bus Collision During Repeated Start Condition (Case 2) 30.6.13.3 Bus Collision During a Stop Condition FIGURE 30-38: Bus Collision During a Stop Condition (Case 1) FIGURE 30-39: Bus Collision During a Stop Condition (Case 2) 30.7 Baud Rate Generator FIGURE 30-40: Baud Rate Generator Block Diagram TABLE 30-2: MSSP Clock Rate w/BRG 30.8 Register Definitions: MSSP Control Register 30-1: SSP1STAT: SSP1 STATUS Register Register 30-2: SSP1CON1: SSP1 Control Register 1 Register 30-3: SSP1CON2: SSP1 Control Register 2 (I2C Mode Only)(1) Register 30-4: SSP1CON3: SSP1 Control Register 3 Register 30-5: SSP1MSK: SSP1 Mask Register Register 30-6: SSP1ADD: SSP1 Address and Baud Rate Register (I2C Mode) Register 30-7: SSP1BUF: SSP1 Buffer Register TABLE 30-3: Summary of Registers Associated with MSSP1 31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1) FIGURE 31-1: EUSART1 Transmit Block Diagram FIGURE 31-2: EUSART1 Receive Block Diagram 31.1 EUSART1 Asynchronous Mode 31.1.1 EUSART1 Asynchronous Transmitter 31.1.1.1 Enabling the Transmitter 31.1.1.2 Transmitting Data 31.1.1.3 Transmit Data Polarity 31.1.1.4 Transmit Interrupt Flag 31.1.1.5 TSR Status 31.1.1.6 Transmitting 9-bit Characters 31.1.1.7 Asynchronous Transmission Set-up FIGURE 31-3: Asynchronous Transmission FIGURE 31-4: Asynchronous Transmission (Back-to-Back) 31.1.2 EUSART1 Asynchronous Receiver 31.1.2.1 Enabling the Receiver 31.1.2.2 Receiving Data 31.1.2.3 Receive Interrupts 31.1.2.4 Receive Framing Error 31.1.2.5 Receive Overrun Error 31.1.2.6 Receiving 9-bit Characters 31.1.2.7 Address Detection 31.1.2.8 Asynchronous Reception Setup 31.1.2.9 9-bit Address Detection Mode Setup FIGURE 31-5: Asynchronous Reception 31.2 Clock Accuracy with Asynchronous Operation 31.3 EUSART1 Baud Rate Generator (BRG) EXAMPLE 31-1: Calculating Baud Rate Error 31.3.1 Auto-Baud Detect TABLE 31-1: BRG Counter Clock Rates FIGURE 31-6: Automatic Baud Rate Calibration 31.3.2 Auto-Baud Overflow 31.3.3 Auto-Wake-up on Break 31.3.3.1 Special Considerations FIGURE 31-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 31-8: Auto-Wake-up Bit (WUE) Timings During Sleep 31.3.4 Break Character Sequence 31.3.4.1 Break and Sync Transmit Sequence 31.3.5 Receiving a Break Character FIGURE 31-9: Send Break Character Sequence 31.4 EUSART1 Synchronous Mode 31.4.1 Synchronous Master Mode 31.4.1.1 Master Clock 31.4.1.2 Clock Polarity 31.4.1.3 Synchronous Master Transmission 31.4.1.4 Synchronous Master Transmission Set-up FIGURE 31-10: Synchronous Transmission FIGURE 31-11: Synchronous Transmission (through TXEN) 31.4.1.5 Synchronous Master Reception 31.4.1.6 Slave Clock 31.4.1.7 Receive Overrun Error 31.4.1.8 Receiving 9-bit Characters 31.4.1.9 Synchronous Master Reception Set-up FIGURE 31-12: Synchronous Reception (Master Mode, SREN) 31.4.2 Synchronous Slave Mode 31.4.2.1 EUSART1 Synchronous Slave Transmit 31.4.2.2 Synchronous Slave Transmission Set-up 31.4.2.3 EUSART1 Synchronous Slave Reception 31.4.2.4 Synchronous Slave Reception Set-up 31.5 EUSART1 Operation During Sleep 31.5.1 Synchronous Receive During Sleep 31.5.2 Synchronous Transmit During Sleep 31.6 Register Definitions: EUSART1 Control Register 31-1: TX1STA: Transmit Status and Control Register Register 31-2: RC1STA: Receive Status and Control Register Register 31-3: BAUD1CON: Baud Rate Control Register Register 31-4: RC1REG(1): Receive Data Register Register 31-5: TX1REG(1): Transmit Data Register Register 31-6: SP1BRGL(1): Baud Rate Generator Register Register 31-7: SP1BRGH(1, 2): Baud Rate Generator High Register TABLE 31-2: Summary of Registers Associated with EUSART1 TABLE 31-3: Baud Rate Formulas TABLE 31-4: Baud Rate for Asynchronous Modes 32.0 Reference Clock Output Module 32.1 Clock Source 32.1.1 Clock Synchronization 32.2 Programmable Clock Divider 32.3 Selectable Duty Cycle 32.4 Operation in Sleep Mode FIGURE 32-1: Clock Reference Block Diagram FIGURE 32-2: Clock Reference Timing Register 32-1: CLKRCON: Reference Clock Control Register TABLE 32-1: Summary of Registers Associated with Clock Reference Output 33.0 In-Circuit Serial Programming™ (ICSP™) 33.1 High-Voltage Programming Entry Mode 33.2 Low-Voltage Programming Entry Mode 33.3 Common Programming Interfaces FIGURE 33-1: ICD RJ-11 Style Connector Interface FIGURE 33-2: PICkit™ Programmer Style Connector Interface FIGURE 33-3: Typical Connection for ICSP™ Programming 34.0 Instruction Set Summary 34.1 Read-Modify-Write Operations TABLE 34-1: Opcode Field Descriptions TABLE 34-2: Abbreviation Descriptions FIGURE 34-1: General Format for Instructions TABLE 34-3: PIC16(L)F18324/18344 Instruction Set 34.2 Instruction Descriptions 35.0 Electrical Specifications 35.1 Absolute Maximum Ratings(†) 35.2 Standard Operating Conditions FIGURE 35-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F18324/18344 Only FIGURE 35-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF18324/18344 Only 35.3 DC Characteristics TABLE 35-1: Supply Voltage FIGURE 35-3: POR and POR ReARM with Slow Rising Vdd TABLE 35-2: Supply Current (Idd)(1,2) TABLE 35-3: Power-down Currents (Ipd)(1,2,3) TABLE 35-4: I/O Ports TABLE 35-5: Memory Specifications TABLE 35-6: Thermal Characteristics 35.4 AC Characteristics FIGURE 35-4: Load Conditions FIGURE 35-5: Clock Timing TABLE 35-7: External Clock/Oscillator Timing Requirements TABLE 35-8: Internal Oscillator Parameters(1) FIGURE 35-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 35-9: PLL Clock Timing Specifications FIGURE 35-7: CLKOUT and I/O Timing TABLE 35-10: CLKOUT and I/O Timing Specifications FIGURE 35-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 35-9: Brown-out Reset Timing and Characteristics TABLE 35-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low Power Brown-Out Reset Specifications TABLE 35-12: Analog-to-Digital Converter (ADC) Characteristics(1,2) TABLE 35-13: Analog-to Digital Converter (ADC) Conversion Timing Specifications(1,2) FIGURE 35-10: ADC Conversion Timing (ADC Clock Fosc-Based) FIGURE 35-11: ADC Conversion Timing (ADC Clock from ADCRC) TABLE 35-14: Comparator Specifications TABLE 35-15: Digital-to-Analog Converter (DAC) Specifications TABLE 35-16: Fixed Voltage Reference (FVR) Specifications FIGURE 35-12: Timer0 and Timer1 External Clock Timings TABLE 35-17: Timer0 and Timer1 External Clock Requirements FIGURE 35-13: Capture/Compare/PWM (CCP) Timings TABLE 35-18: Capture/Compare/PWM (CCP) Characteristics FIGURE 35-14: CLC Propagation Timing TABLE 35-19: Configurable Logic Cell (CLC) Characteristics FIGURE 35-15: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 35-20: EUSART Synchronous Transmission Characteristics FIGURE 35-16: EUSART Synchronous Receive (Master/Slave) Timing TABLE 35-21: EUSART Synchronous Receive Characteristics FIGURE 35-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 35-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 35-19: SPI Slave Mode Timing (CKE = 0) FIGURE 35-20: SPI Slave Mode Timing (CKE = 1) TABLE 35-22: SPI Mode Characteristics FIGURE 35-21: I2C Bus Start/Stop Bits Timing TABLE 35-23: I2C Bus Start/Stop Bits Characteristics FIGURE 35-22: I2C Bus Data Timing TABLE 35-24: I2C Bus Data Characteristics 36.0 DC and AC Characteristics Graphs and Charts 37.0 Development Support 37.1 MPLAB X Integrated Development Environment Software 37.2 MPLAB XC Compilers 37.3 MPASM Assembler 37.4 MPLINK Object Linker/ MPLIB Object Librarian 37.5 MPLAB Assembler, Linker and Librarian for Various Device Families 37.6 MPLAB X SIM Software Simulator 37.7 MPLAB REAL ICE In-Circuit Emulator System 37.8 MPLAB ICD 3 In-Circuit Debugger System 37.9 PICkit 3 In-Circuit Debugger/ Programmer 37.10 MPLAB PM3 Device Programmer 37.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 37.12 Third-Party Development Tools 38.0 Packaging Information 38.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 38.2 Package Details Appendix A: Data Sheet Revision History Revision D (11/2018) Revision C (07/2017) Revision B (11/2016) Revision A (7/2015) The Microchip WebSite Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales and Service