Datasheet PIC16F15313, PIC16F15323, PIC16LF15313, PIC16LF15323 (Microchip) - 7

 2017
TABLE 4: 14/16-PIN ALLOCATION TABLE (PIC16(L)F15323)
-2019 Microchip
OP FN ce tor T R pt (2) OIC/TSS G S O M ren ara SP D C K rru sic I/O ADC fe NC DAC imers ZC SAR CL T CCP PW CW MS CL EU Inte Pull-up Ba
Technology In
in QFN/UQ Re Comp in PDIP/ 16-P 14-P
RA0 13 12 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― ― ― ― IOCA0 Y ICSPDAT RA1 12 11 ANA1 V ― DAC1 c. REF+ C1IN0- REF+ T0CKI
(1)
― ― ― ― ― ― ― ― IOCA1 Y ICSPCLK C2IN0- RA2 11 10 ANA2 ― ― ― ― ― ― ― CWG1IN
(1)
― ZCD1 ― ― ― INT
(1)
Y ― IOCA2 RA3 4 3 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCA3 Y MCLR VPP RA4 3 2 ANA4 ― ― ― ― T1G
(1)
― ― ― ― ― ― ― ― IOCA4 Y CLKOUT OSC2 RA5 2 1 ANA5 ― ― ― ― T1CKI
(1)
― ― ― ― ― CLCIN3
(1)
― IOCA5 Y CLKIN T2IN OSC1 EIN RC0 10 9 ANC0 ― C2IN0+ ― ― ― ― ― ― SCK1
(1)
― ― ― ― IOCC0 Y ― SCL1
(1,4)
RC1 9 8 ANC1 ― C1IN1- ― ― ― ― ― ― SDA1
(1,4)
― ― CLCIN2
(1)
― IOCC1 Y ― C2IN1- SDI1
(1) PIC16(L)F15313/23
RC2 8 7 ANC2 ― C1IN2- ― ― ― ― ― ― ― ― ― ― ― IOCC2 Y ― C2IN2- RC3 7 6 ANC3 ― C1IN3- ― ― ― CCP2
(1)
― ― SS1
(1)
― ― CLCIN0
(1)
― IOCC3 Y ― C2IN3- RC4 6 5 ANC4 ― ― ― ― ― ― ― ― ― ― TX1
(1)
CLCIN1
(1)
― IOCC4 Y ― CK1
(1)
RC5 5 4 ANC5 ― ― ― ― ― CCP1
(1)
― ― ― ― RX1
(1)
― ― IOCC5 Y ― DT1
(1)
VDD 1 16 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD VSS 14 13 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS
Note 1:
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. D S
2:
All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. 40001897B-
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C logic levels. PPS assignments to the other pins wil operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. page 7 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Cont.) Analog Peripherals Flexible Oscillator Structure Pin Diagrams Pin Allocation Tables Table of Contents Most Current Data Sheet Errata Customer Notification System Full-Featured 8/14-Pin Microcontrollers 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit Naming Conventions FIGURE 1-1: PIC16(L)F15313 Block Diagram FIGURE 1-2: PIC16(L)F15323 Block Diagram TABLE 1-2: PIC16(L)F15313 Pinout Description TABLE 1-3: PIC16(L)F15323 Pinout Description 2.0 Guidelines for Getting Started with PIC16(L)F15313/23 Microcontrollers 2.1 Basic Connection Requirements FIGURE 2-1: Recommended Minimum Connections 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin FIGURE 2-2: Example of MCLR Pin Connections 2.4 ICSP™ Pins 2.5 External Oscillator Pins 2.6 Unused I/Os FIGURE 2-3: Suggested Placement of the Oscillator Circuit 3.0 Enhanced Mid-Range CPU FIGURE 3-1: Core Data Path Diagram 3.1 Automatic Interrupt Context Saving 3.2 16-Level Stack with Overflow and Underflow 3.3 File Select Registers 3.4 Instruction Set 4.0 Memory Organization 4.1 Program Memory Organization TABLE 4-1: Device Sizes and Addresses FIGURE 4-1: Program Memory Map And Stack For PIC16(L)F15313/23 EXAMPLE 4-1: RETLW Instruction EXAMPLE 4-2: Accessing Program Memory Via FSR 4.2 Memory Access Partition (MAP) TABLE 4-2: Memory Access Partition 4.3 Data Memory Organization FIGURE 4-2: Banked Memory Partitioning TABLE 4-3: Core Registers Register 4-1: STATUS: STATUS Register TABLE 4-4: PIC16(L)F15313/23 Memory Map, Banks 0-7 TABLE 4-5: PIC16(L)F15313/23 Memory Map, Banks 8-15 TABLE 4-6: PIC16(L)F15313/23 Memory Map, Banks 16-23 TABLE 4-7: PIC16(L)F15313/23 Memory Map, Banks 56-63 TABLE 4-8: PIC16(L)F15313/23 Memory Map, Banks 60, 61, 62, and 63 TABLE 4-9: Special Function Register Summary Banks 0-63 (All Banks) TABLE 4-10: Special Function Register Summary Banks 0-63 4.4 PCL and PCLATH FIGURE 4-3: Loading Of PC In Different Situations 4.5 Stack FIGURE 4-4: Accessing the Stack Example 1 FIGURE 4-5: Accessing the Stack Example 2 FIGURE 4-6: Accessing the Stack Example 3 FIGURE 4-7: Accessing the Stack Example 4 4.6 Indirect Addressing FIGURE 4-8: Indirect Addressing PIC16(L)F15313/23 FIGURE 4-9: Traditional/Banked Data Memory Map FIGURE 4-10: Linear Data Memory Map FIGURE 4-11: Program Flash Memory Map 5.0 Device Configuration 5.1 Configuration Words 5.2 Register Definitions: Configuration Words Register 5-1: Configuration Word 1: Oscillators Register 5-2: Configuration Word 2: Supervisors Register 5-3: Configuration Word 3: Windowed Watchdog Register 5-4: Configuration Word 4: Memory TABLE 5-1: Boot Block Size Bits Register 5-5: Configuration Word 5: Code Protection 5.3 Code Protection 5.4 Write Protection 5.5 User ID 5.6 Device ID and Revision ID 5.7 Register Definitions: Device and Revision Register 5-6: DevID: Device ID Register Register 5-7: RevisionID: Revision ID Register 6.0 Device Information Area TABLE 6-1: Device Information Area 6.1 Microchip Unique identifier (MUI) 6.2 External Unique Identifier (EUI) 6.3 Analog-to-Digital Conversion Data of the Temperature Sensor 6.4 Fixed Voltage Reference Data 7.0 Device Configuration Information TABLE 7-1: Device Configuration Information for PIC16(L)F15313/23 Devices 7.1 DIA and DCI Access 8.0 Resets FIGURE 8-1: Simplified Block Diagram of On-Chip Reset Circuit 8.1 Power-on Reset (POR) 8.2 Brown-out Reset (BOR) TABLE 8-1: BOR Operating Modes FIGURE 8-2: Brown-out Situations 8.3 Register Definitions: Brown-out Reset Control Register 8-1: BORCON: Brown-out Reset Control Register 8.4 Low-Power Brown-out Reset (LPBOR) 8.5 MCLR TABLE 8-2: MCLR Configuration 8.6 Windowed Watchdog Timer (WWDT) Reset 8.7 RESET Instruction 8.8 Stack Overflow/Underflow Reset 8.9 Programming Mode Exit 8.10 Power-up Timer 8.11 Start-up Sequence FIGURE 8-3: Reset Start-up Sequence 8.12 Memory Execution Violation 8.13 Determining the Cause of a Reset TABLE 8-3: Reset Status Bits and Their Significance TABLE 8-4: Reset Condition for Special Registers 8.14 Power Control (PCONx) Registers 8.15 Register Definitions: Power Control Register 8-2: PCON0: Power Control Register 0 Register 8-3: PCON1: Power Control Register 0 TABLE 8-5: Summary of Registers Associated with Resets 9.0 Oscillator Module (with Fail-Safe Clock Monitor) 9.1 Overview FIGURE 9-1: Simplified PIC® MCU Clock Source Block Diagram 9.2 Clock Source Types FIGURE 9-2: External Clock (EC) Mode Operation FIGURE 9-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 9-4: Ceramic Resonator Operation (XT or HS Mode) 9.3 Clock Switching FIGURE 9-5: Clock Switch (CSWHOLD = 0) FIGURE 9-6: Clock Switch (CSWHOLD = 1) FIGURE 9-7: Clock Switch Abandoned 9.4 Fail-Safe Clock Monitor FIGURE 9-8: FSCM Block Diagram FIGURE 9-9: FSCM Timing Diagram 9.5 Register Definitions: Oscillator Control Register 9-1: OSCCON1: Oscillator Control Register1 Register 9-2: OSCCON2: Oscillator Control Register 2 TABLE 9-1: NOSC/COSC Bit Settings TABLE 9-2: NDIV/CDIV Bit Settings Register 9-3: OSCCON3: Oscillator Control Register 3 Register 9-4: OSCSTAT: Oscillator STATUS Register 1 Register 9-5: OSCEN: Oscillator Manual Enable Register Register 9-6: OSCFRQ: HFINTOSC Frequency Selection Register Register 9-7: OSCTUNE: HFINTOSC Tuning Register TABLE 9-3: Summary of Registers Associated with Clock Sources TABLE 9-4: Summary OF Configuration Word WITH Clock Sources 10.0 Interrupts FIGURE 10-1: Interrupt Logic 10.1 Operation 10.2 Interrupt Latency FIGURE 10-2: Interrupt Latency FIGURE 10-3: INT Pin Interrupt Timing 10.3 Interrupts During Sleep 10.4 INT Pin 10.5 Automatic Context Saving 10.6 Register Definitions: Interrupt Control Register 10-1: INTCON: Interrupt Control Register Register 10-2: PIE0: Peripheral Interrupt Enable Register 0 Register 10-3: PIE1: Peripheral Interrupt Enable Register 1 Register 10-4: PIE2: Peripheral Interrupt Enable Register 2 Register 10-5: PIE3: Peripheral Interrupt Enable Register 3 Register 10-6: PIE4: Peripheral Interrupt Enable Register 4 Register 10-7: PIE5: Peripheral Interrupt Enable Register 5 Register 10-8: PIE6: Peripheral Interrupt Enable Register 6 Register 10-9: PIE7: Peripheral Interrupt Enable Register 7 Register 10-10: PIR0: Peripheral Interrupt Status Register 0 Register 10-11: PIR1: Peripheral Interrupt Request Register 1 Register 10-12: PIR2: Peripheral Interrupt Request Register 2 Register 10-13: PIR3: Peripheral Interrupt Request Register 3 Register 10-14: PIR4: Peripheral Interrupt Request Register 4 Register 10-15: PIR5: Peripheral Interrupt Request Register 5 Register 10-16: PIR6: Peripheral Interrupt Request Register 6 Register 10-17: PIR7: Peripheral Interrupt Request Register 7 TABLE 10-1: Summary of Registers Associated with Interrupts 11.0 Power-Saving Operation Modes 11.1 DOZE Mode FIGURE 11-1: DOZE Mode Operation Example 11.2 Sleep Mode FIGURE 11-2: Wake-Up From Sleep Through Interrupt 11.3 IDLE Mode 11.4 Register Definitions: Voltage Regulator and DOZE Control Register 11-1: VREGCON: Voltage Regulator Control Register(1) Register 11-2: CPUDOZE: Doze and Idle Register TABLE 11-1: Summary of Registers Associated with Power-Down Mode 12.0 Windowed Watchdog Timer (WWDT) FIGURE 12-1: Watchdog Timer Block Diagram 12.1 Independent Clock Source 12.2 WDT Operating Modes TABLE 12-1: WDT Operating Modes 12.3 Time-Out Period 12.4 Watchdog Window 12.5 Clearing the WDT 12.6 Operation During Sleep TABLE 12-2: WDT Clearing Conditions FIGURE 12-2: Window Period and Delay 12.7 Register Definitions: Windowed Watchdog Timer Control Register 12-1: WDTCON0: Watchdog Timer Control Register 0 Register 12-2: WDTCON1: Watchdog Timer Control Register 1 Register 12-3: WDTPSL: WDT Prescale Select Low Byte Register Register 12-4: WDTPSH: WDT Prescale Select High Byte Register Register 12-5: WDTTMR: WDT Timer Register TABLE 12-3: Summary of Registers Associated with Watchdog Timer TABLE 12-4: Summary OF Configuration Word WITH Watchdog Timer 13.0 Nonvolatile Memory (NVM) Control 13.1 Program Flash Memory (PFM) TABLE 13-1: Flash Memory Organization by Device 13.2 FSR and INDF Access 13.3 NVMREG Access FIGURE 13-1: Flash Program Memory Read Flowchart EXAMPLE 13-1: Program Memory Read FIGURE 13-2: NVM Unlock Sequence Flowchart EXAMPLE 13-2: NVM Unlock Sequence FIGURE 13-3: NVM Erase Flowchart EXAMPLE 13-3: Erasing One Row of Program Flash Memory (PFM) TABLE 13-2: NVM Organization and Access Information FIGURE 13-4: NVMREGS Writes to Program Flash Memory With 32 write latches FIGURE 13-5: Program Flash Memory Write Flowchart EXAMPLE 13-4: Writing to Program Flash Memory FIGURE 13-6: Flash Program Memory Modify Flowchart TABLE 13-3: NVMREGS Access to Device Information Area, Device Configuration Area, User ID, Device ID and Configuration Words (NVMREGS = 1) EXAMPLE 13-5: Device ID Access FIGURE 13-7: Flash Program Memory Verify Flowchart TABLE 13-4: Actions for PFM When WR = 1 13.4 Register Definitions: Flash Program Memory Control Register 13-1: NVMDATL: Nonvolatile Memory Data Low Byte Register Register 13-2: NVMDATH: Nonvolatile Memory Data High Byte Register Register 13-3: NVMADRL: Nonvolatile Memory Address Low Byte Register Register 13-4: NVMADRH: Nonvolatile Memory Address High Byte Register Register 13-5: NVMCON1: Nonvolatile Memory Control 1 Register Register 13-6: NVMCON2: NONVOLATILE Memory Control 2 Register TABLE 13-5: Summary of Registers Associated with Nonvolatile Memory (NVM) 14.0 I/O Ports TABLE 14-1: Port Availability Per Device FIGURE 14-1: Generic I/O Port Operation 14.1 I/O Priorities 14.2 PORTA Registers EXAMPLE 14-1: Initializing PORTA 14.3 Register Definitions: PORTA Register 14-1: PORTA: PORTA Register Register 14-2: TRISA: PORTA Tri-State Register Register 14-3: LATA: PORTA Data Latch Register Register 14-4: ANSELA: PORTA Analog Select Register Register 14-5: WPUA: Weak Pull-Up PORTA Register Register 14-6: ODCONA: PORTA Open-Drain Control Register Register 14-7: SLRCONA: PORTA Slew Rate Control Register Register 14-8: INLVLA: PORTA Input Level Control Register TABLE 14-2: Summary of Registers Associated with PORTA 14.4 PORTC Registers (PIC16(L)F15323 only) 14.5 Register Definitions: PORTC Register 14-9: PORTC: PORTC Register Register 14-10: TRISC: PORTC Tri-State Register Register 14-11: LATC: PORTC Data Latch Register Register 14-12: ANSELC: PORTC Analog Select Register Register 14-13: WPUC: Weak Pull-Up PORTC Register Register 14-14: ODCONC: PORTC Open-Drain Control Register Register 14-15: SLRCONC: PORTC Slew Rate Control Register Register 14-16: INLVLC: PORTC Input Level Control Register TABLE 14-3: Summary of Registers Associated with PORTC 15.0 Peripheral Pin Select (PPS) Module FIGURE 15-1: Simplified PPS Block Diagram 15.1 PPS Inputs 15.2 PPS Outputs TABLE 15-1: PPS Input Signal Routing Options (PIC16(L)F15313) TABLE 15-2: PPS Input Signal Routing Options (PIC16(L)F15323) TABLE 15-3: PPS Input Register Values 15.3 Bidirectional Pins 15.4 PPS Lock EXAMPLE 15-1: PPS Lock/Unlock sequence 15.5 PPS Permanent Lock 15.6 Operation During Sleep 15.7 Effects of a Reset TABLE 15-4: PPS Output Signal Routing Options (PIC16(L)F15313) TABLE 15-5: PPS Output Signal Routing Options (PIC16(L)F15323) 15.8 Register Definitions: PPS Input Selection Register 15-1: xxxPPS: Peripheral xxx input Selection(1) Register 15-2: RxyPPS: Pin Rxy Output Source Selection Register Register 15-3: PPSLOCK: PPS Lock Register TABLE 15-6: Summary of Registers Associated with the PPS Module 16.0 Peripheral Module Disable 16.1 Disabling a Module 16.2 Enabling a module 16.3 Disabling a Module 16.4 System Clock Disable Register 16-1: PMD0: PMD Control Register 0 Register 16-2: PMD1: PMD Control Register 1 Register 16-3: PMD2: PMD Control Register 2 Register 16-4: PMD3: PMD Control Register 3 Register 16-5: PMD4: PMD Control Register 4 Register 16-6: PMD5 – PMD Control Register 5 TABLE 16-1: Summary of Registers Associated with the PPS Module 17.0 Interrupt-On-Change 17.1 Enabling the Module 17.2 Individual Pin Configuration 17.3 Interrupt Flags EXAMPLE 17-1: Clearing Interrupt Flags (PORTA Example) 17.4 Operation in Sleep FIGURE 17-1: Interrupt-On-Change Block Diagram (PORTA Example) 17.5 Register Definitions: Interrupt-on-Change Control Register 17-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 17-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 17-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 17-4: IOCCP: Interrupt-on-Change PORTC Positive Edge Register(1) Register 17-5: IOCCN: Interrupt-on-Change PORTC Negative Edge Register(1) Register 17-6: IOCCF: Interrupt-on-Change PORTC Flag Register(1) TABLE 17-1: Summary of Registers Associated with Interrupt-On-Change 18.0 Fixed Voltage Reference (FVR) 18.1 Independent Gain Amplifiers 18.2 FVR Stabilization Period FIGURE 18-1: Voltage Reference Block Diagram 18.3 Register Definitions: FVR Control Register 18-1: FVRCON: Fixed Voltage Reference Control Register TABLE 18-1: Summary of Registers Associated with Fixed Voltage Reference 19.0 Temperature Indicator Module 19.1 Module Operation FIGURE 19-1: Temperature Indicator Module Block Diagram TABLE 19-1: Recommended Vdd vs. Range 19.2 Temperature Calculation EQUATION 19-1: Sensor Temperature 19.3 ADC Acquisition Time TABLE 19-2: Summary of Registers Associated with the Temperature Indicator(1) 20.0 Analog-to-Digital Converter (ADC) Module FIGURE 20-1: ADC Block Diagram 20.1 ADC Configuration TABLE 20-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 20-2: Analog-to-Digital Conversion Tad Cycles FIGURE 20-3: 10-bit ADC Conversion Result Format 20.2 ADC Operation TABLE 20-2: ADC Auto-Conversion Table EXAMPLE 20-1: ADC Conversion 20.3 ADC Acquisition Requirements EQUATION 20-1: Acquisition Time Example FIGURE 20-4: Analog Input Model FIGURE 20-5: ADC Transfer Function 20.4 Register Definitions: ADC Control Register 20-1: ADCON0: ADC Control Register 0 Register 20-2: ADCON1: ADC Control Register 1 Register 20-3: ADACT: A/D Auto-Conversion Trigger Register 20-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 20-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 20-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 20-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 TABLE 20-3: Summary of Registers Associated with ADC 21.0 5-Bit Digital-to-Analog Converter (DAC1) Module 21.1 Output Voltage Selection EQUATION 21-1: DAC Output Voltage 21.2 Ratiometric Output Level 21.3 DAC Voltage Reference Output FIGURE 21-1: Digital-to-Analog Converter Block Diagram FIGURE 21-2: Voltage Reference Output Buffer Example 21.4 Operation During Sleep 21.5 Effects of a Reset 21.6 Register Definitions: DAC Control Register 21-1: DAC1CON0: Voltage Reference Control Register 0 Register 21-2: DAC1CON1: Voltage Reference Control Register 1 TABLE 21-1: Summary of Registers Associated with the DAC1 Module 22.0 Numerically Controlled Oscillator (NCO) Module FIGURE 22-1: Numerically Controlled Oscillator Module Simplified Block Diagram 22.1 NCO OPERATION EQUATION 22-1: NCO Overflow Frequency 22.2 FIXED DUTY CYCLE MODE 22.3 PULSE FREQUENCY MODE 22.4 OUTPUT POLARITY CONTROL 22.5 Interrupts 22.6 Effects of a Reset 22.7 Operation in Sleep FIGURE 22-2: FDC Output Mode Operation Diagram 22.8 NCO Control Registers Register 22-1: NCO1CON: NCO Control Register Register 22-2: NCO1CLK: NCO1 Input Clock Control Register Register 22-3: NCO1ACCL: NCO1 Accumulator Register – Low Byte Register 22-4: NCO1ACCH: NCO1 Accumulator Register – High Byte Register 22-5: NCO1ACCU: NCO1 Accumulator Register – Upper Byte(1) Register 22-6: NCO1INCL: NCO1 Increment Register – Low Byte(1,2) Register 22-7: NCO1INCH: NCO1 Increment Register – High Byte(1) Register 22-8: NCO1INCU: NCO1 Increment Register – Upper Byte(1) TABLE 22-1: Summary of Registers Associated with NCO 23.0 Comparator Module 23.1 Comparator Overview TABLE 23-1: Available Comparators FIGURE 23-1: Single Comparator FIGURE 23-2: Comparator Module Simplified Block Diagram 23.2 Comparator Control TABLE 23-2: Comparator Output State vs. Input Conditions 23.3 Comparator Hysteresis 23.4 Timer1 Gate Operation 23.5 Comparator Interrupt 23.6 Comparator Positive Input Selection 23.7 Comparator Negative Input Selection 23.8 Comparator Response Time 23.9 Analog Input Connection Considerations FIGURE 23-3: Analog Input Model 23.10 CWG1 Auto-shutdown Source 23.11 Operation in Sleep Mode 23.12 Register Definitions: Comparator Control Register 23-1: CMxCON0: Comparator Cx Control Register 0 Register 23-2: CMxCON1: Comparator Cx Control Register 1 Register 23-3: CMxNCH: Comparator Cx Negative Input Select Register Register 23-4: CMxPCH: Comparator Cx Positive Input Select Register Register 23-5: CMOUT: Comparator Output Register TABLE 23-3: Summary of Registers Associated with Comparator Module 24.0 Zero-Cross Detection (ZCD) Module 24.1 External Resistor Selection EQUATION 24-1: External Resistor FIGURE 24-1: External Voltage FIGURE 24-2: Simplified ZCD Block Diagram 24.2 ZCD Logic Output 24.3 ZCD Logic Polarity 24.4 ZCD Interrupts 24.5 Correcting for Vcpinv offset EQUATION 24-2: R-C Calculations EXAMPLE 24-1: EQUATION 24-3: ZCD Event Offset EQUATION 24-4: ZCD Pull-up/down 24.6 Handling Vpeak variations EQUATION 24-5: Series R for V range 24.7 Operation During Sleep 24.8 Effects of a Reset 24.9 Register Definitions: ZCD Control Register 24-1: ZCDCON: Zero-Cross Detection Control Register TABLE 24-1: Summary of Registers Associated with the ZCD Module TABLE 24-2: Summary of Configuration Word with the ZCD Module 25.0 Timer0 Module 25.1 Timer0 Operation 25.2 Clock Source Selection 25.3 Programmable Prescaler 25.4 Programmable Postscaler 25.5 Operation during Sleep 25.6 Timer0 Interrupts 25.7 Timer0 Output FIGURE 25-1: Block Diagram of Timer0 Register 25-1: T0CON0: TIMER0 Control Register 0 Register 25-2: T0CON1: TIMER0 Control Register 1 TABLE 25-1: Summary of Registers Associated with Timer0 26.0 Timer1 Module with Gate Control FIGURE 26-1: Timer1 Block Diagram 26.1 Timer1 Operation TABLE 26-1: Timer1 Enable Selections 26.2 Clock Source Selection 26.3 Timer Prescaler 26.4 Timer Operation in Asynchronous Counter Mode 26.5 Timer Gate TABLE 26-2: Timer Gate Enable Selections 26.6 Timer1 Interrupts 26.7 Timer1 Operation During Sleep 26.8 CCP Capture/Compare Time Base 26.9 CCP Auto-Conversion Trigger FIGURE 26-2: Timer1 Incrementing Edge FIGURE 26-3: Timer1 Gate Enable Mode FIGURE 26-4: Timer1 Gate Toggle Mode FIGURE 26-5: Timer1 Gate Single-Pulse Mode FIGURE 26-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 26.10 Register Definitions: Timer1 Control Register 26-1: T1CON: Timer1 Control Register Register 26-2: T1GCON: Timer1 Gate Control Register Register 26-3: T1CLK Timer1 Clock Select Register Register 26-4: T1GATE Timer1 Gate Select Register TABLE 26-3: Summary of Registers Associated with Timer1 27.0 Timer2 Module With Hardware Limit Timer (HLT) FIGURE 27-1: Timer2 Block Diagram FIGURE 27-2: Timer2 Clock Source Block Diagram 27.1 Timer2 Operation 27.2 Timer2 Output 27.3 External Reset Sources TABLE 27-1: Timer2 Operating Modes 27.4 Timer2 Interrupt FIGURE 27-3: Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram 27.5 Operation Examples FIGURE 27-4: Software Gate Mode Timing Diagram (MODE = 00000) FIGURE 27-5: Hardware Gate Mode Timing Diagram (MODE = 00001) FIGURE 27-6: Edge-Triggered Hardware Limit Mode Timing Diagram (MODE = 00100) FIGURE 27-7: Level-Triggered Hardware Limit Mode Timing Diagram (MODE = 00111) FIGURE 27-8: Software Start One-shot Mode Timing Diagram (MODE = 01000) FIGURE 27-9: Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001) FIGURE 27-10: Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100) FIGURE 27-11: Low Level Reset, Edge-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 01110) FIGURE 27-12: Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001) FIGURE 27-13: Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110) 27.6 Timer2 Operation During Sleep 27.7 Register Definitions: Timer2 Control Register 27-1: T2CLKCON: Timer2 Clock Selection Register Register 27-2: T2CON: Timer2 Control Register Register 27-3: T2HLT: Timerx Hardware Limit Control Register Register 27-4: T2RST: Timer2 External Reset Signal Selection Register TABLE 27-2: Summary of Registers Associated with Timer2 28.0 Capture/Compare/PWM Modules TABLE 28-1: Available CCP Modules 28.1 Capture Mode FIGURE 28-1: Capture Mode Operation Block Diagram EXAMPLE 28-1: Changing Between Capture Prescalers 28.2 Compare Mode FIGURE 28-2: Compare Mode Operation Block Diagram 28.3 PWM Overview FIGURE 28-3: CCP PWM Output Signal FIGURE 28-4: Simplified PWM Block Diagram EQUATION 28-1: PWM Period FIGURE 28-5: PWM 10-Bit Alignment EQUATION 28-2: Pulse Width EQUATION 28-3: Duty Cycle Ratio EQUATION 28-4: PWM Resolution TABLE 28-2: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 28-3: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 28.4 Register Definitions: CCP Control TABLE 28-4: Long Bit Names Prefixes for CCP Peripherals Register 28-1: CCPxCON: CCPx Control Register Register 28-2: CCPxCAP: Capture Input Selection Register Register 28-3: CCPRxL Register: CCPx Register Low Byte Register 28-4: CCPRxH Register: CCPx Register High Byte TABLE 28-5: Summary Of Registers Associated with CCPx 29.0 Pulse-Width Modulation (PWM) FIGURE 29-1: PWM Output 29.1 Standard PWM Mode FIGURE 29-2: Simplified PWM Block Diagram EQUATION 29-1: PWM Period EQUATION 29-2: Pulse Width EQUATION 29-3: Duty Cycle Ratio EQUATION 29-4: PWM Resolution TABLE 29-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 29-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 29.2 Register Definitions: PWM Control Register 29-1: PWMxCON: PWM Control Register Register 29-2: PWMXDCH: PWM Duty Cycle High Bits Register 29-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 29-3: Summary of Registers Associated with PWMx 30.0 Complementary Waveform Generator (CWG) Module TABLE 30-1: Available CWG Modules 30.1 Fundamental Operation FIGURE 30-1: Simplified CWG Block Diagram (Half-Bridge Mode) FIGURE 30-2: Simplified CWG Block Diagram (Push-Pull Mode) FIGURE 30-3: Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) FIGURE 30-4: Simplified CWG Block Diagram (Output Steering Modes) 30.2 Clock Source 30.3 Selectable Input Sources TABLE 30-2: Selectable Input Sources 30.4 Output Control FIGURE 30-5: CWG Output Block Diagram 30.5 Dead-Band Control 30.6 Rising Edge and Reverse Dead Band 30.7 Falling Edge and Forward Dead Band FIGURE 30-6: Dead-Band Operation CWG1DBR = 0x01, CWG1DBF = 0x02 FIGURE 30-7: Dead-Band Operation, CWG1DBR = 0x03, CWG1DBF = 0x04, Source Shorter Than Dead Band 30.8 Dead-Band Uncertainty EQUATION 30-1: Dead-Band Uncertainty FIGURE 30-8: Example of PWM Direction Change FIGURE 30-9: CWG Half-Bridge Mode Operation 30.9 CWG Steering Mode FIGURE 30-10: Example of Asynchronous Steering Event (MODE<2:0> = 000) FIGURE 30-11: Example of Steering Event (MODE<2:0> = 001) 30.10 Auto-Shutdown 30.11 Operation During Sleep FIGURE 30-12: CWG Shutdown Block Diagram 30.12 Configuring the CWG FIGURE 30-13: Shutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = 01, LSBD = 01) FIGURE 30-14: Shutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = 01, LSBD = 01) 30.13 Register Definitions: CWG Control Register 30-1: CWG1CON0: CWG1 Control Register 0 Register 30-2: CWG1CON1: CWG1 Control Register 1 Register 30-3: CWG1DBR: CWG1 Rising Dead-Band Counter Register Register 30-4: CWG1DBF: CWG1 Falling Dead-Band Counter Register Register 30-5: CWG1AS0: CWG1 Auto-Shutdown Control Register 0 Register 30-6: CWG1AS1: CWG1 Auto-Shutdown Control Register 1 Register 30-7: CWG1STR: CWG1 Steering Control Register(1) Register 30-8: CWG1CLK: CWG1 Clock Selection Register Register 30-9: CWG1DAT: CWG1 Input Selection Register TABLE 30-3: Summary of Registers Associated with CWG 31.0 Configurable Logic Cell (CLC) TABLE 31-1: Available CLC Modules FIGURE 31-1: CLCx Simplified Block Diagram 31.1 CLCx Setup TABLE 31-2: CLCx Data Input Selection TABLE 31-3: Data Gating Logic 31.2 CLCx Interrupts 31.3 Output Mirror Copies 31.4 Effects of a Reset 31.5 Operation During Sleep 31.6 CLCx Setup Steps FIGURE 31-2: Input Data Selection and Gating FIGURE 31-3: Programmable Logic Functions 31.7 Register Definitions: CLC Control Register 31-1: CLCxCON: Configurable Logic Cell Control Register Register 31-2: CLCxPOL: Signal Polarity Control Register Register 31-3: CLCxSEL0: Generic CLCx Data 0 Select Register Register 31-4: CLCxSEL1: Generic CLCx Data 1 Select Register Register 31-5: CLCxSEL2: Generic CLCx Data 2 Select Register Register 31-6: CLCxSEL3: Generic CLCx Data 3 Select Register Register 31-7: CLCxGLS0: Gate 0 Logic Select Register Register 31-8: CLCxGLS1: Gate 1 Logic Select Register Register 31-9: CLCxGLS2: Gate 2 Logic Select Register Register 31-10: CLCxGLS3: Gate 3 Logic Select Register Register 31-11: CLCDATA: CLC Data Output TABLE 31-4: Summary of Registers Associated with CLCx 32.0 Master Synchronous Serial Port (MSSP1) Module 32.1 MSSP Module Overview FIGURE 32-1: MSSP Block Diagram (SPI mode) FIGURE 32-2: MSSP Block Diagram (I2C Master mode) FIGURE 32-3: MSSP Block Diagram (I2C Slave mode) 32.2 SPI Mode Overview FIGURE 32-4: SPI Master and Multiple Slave Connection FIGURE 32-5: SPI Master/Slave Connection FIGURE 32-6: SPI Mode Waveform (Master Mode) FIGURE 32-7: SPI Daisy-Chain Connection FIGURE 32-8: Slave Select Synchronous Waveform FIGURE 32-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 32-10: SPI Mode Waveform (Slave Mode with CKE = 1) 32.3 I2C Mode Overview FIGURE 32-11: I2C Master/ Slave Connection 32.4 I2C Mode Operation TABLE 32-1: I2C Bus terms FIGURE 32-12: I2C Start and Stop Conditions FIGURE 32-13: I2C Restart Condition 32.5 I2C Slave Mode Operation FIGURE 32-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 32-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 32-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 32-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 32-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) FIGURE 32-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 32-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 32-23: Clock Synchronization Timing FIGURE 32-24: Slave Mode General Call Address Sequence 32.6 I2C Master Mode FIGURE 32-25: Baud Rate Generator Timing with Clock Arbitration FIGURE 32-26: First Start Bit Timing FIGURE 32-27: Repeated Start Condition Waveform FIGURE 32-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) FIGURE 32-29: I2C Master Mode Waveform (Reception, 7-bit Address) FIGURE 32-30: Acknowledge Sequence Waveform FIGURE 32-31: Stop Condition Receive or Transmit Mode FIGURE 32-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 32-33: Bus Collision During Start Condition (SDA Only) FIGURE 32-34: Bus Collision During Start Condition (SCL = 0) FIGURE 32-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 32-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 32-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 32-38: Bus Collision During a Stop Condition (Case 1) FIGURE 32-39: Bus Collision During a Stop Condition (Case 2) 32.7 Baud Rate Generator FIGURE 32-40: Baud Rate Generator Block Diagram TABLE 32-2: MSSP Clock Rate w/BRG 32.8 Register Definitions: MSSP1 Control Register 32-1: SSP1STAT: SSP1 STATUS Register Register 32-2: SSP1CON1: SSP1 Control Register 1 Register 32-3: SSP1CON2: SSP1 Control Register 2 (I2C Mode Only)(1) Register 32-4: SSP1CON3: SSP1 Control Register 3 Register 32-5: SSP1MSK: SSP1 Mask Register Register 32-6: SSP1ADD: MSSP1 Address and Baud Rate Register (I2C Mode) Register 32-7: SSP1BUF: MSSP1 Buffer Register TABLE 32-3: Summary of Registers Associated with MSSP1 33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 33-1: EUSART Transmit Block Diagram FIGURE 33-2: EUSART Receive Block Diagram 33.1 EUSART Asynchronous Mode FIGURE 33-3: Asynchronous Transmission FIGURE 33-4: Asynchronous Transmission (Back-to-Back) FIGURE 33-5: Asynchronous Reception 33.2 Clock Accuracy with Asynchronous Operation 33.3 EUSART Baud Rate Generator (BRG) EXAMPLE 33-1: Calculating Baud Rate Error TABLE 33-1: BRG Counter Clock Rates FIGURE 33-6: Automatic Baud Rate Calibration FIGURE 33-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 33-8: Auto-Wake-up Bit (WUE) Timings During Sleep FIGURE 33-9: Send Break Character Sequence 33.4 EUSART Synchronous Mode FIGURE 33-10: Synchronous Transmission FIGURE 33-11: Synchronous Transmission (Through TXEN) FIGURE 33-12: Synchronous Reception (Master Mode, SREN) 33.5 EUSART Operation During Sleep 33.6 Register Definitions: EUSART Control Register 33-1: TX1STA: Transmit Status and Control Register Register 33-2: RC1STA: Receive Status and Control Register Register 33-3: BAUD1CON: Baud Rate Control Register Register 33-4: RC1REG(1): Receive Data Register Register 33-5: TX1REG(1): Transmit Data Register Register 33-6: SP1BRGL(1): Baud Rate Generator Register Register 33-7: SP1BRGH(1, 2): Baud Rate Generator High Register TABLE 33-2: Summary of Registers Associated with EUSART TABLE 33-3: Baud Rate Formulas TABLE 33-4: Baud Rate For Asynchronous Modes 34.0 Reference Clock Output Module 34.1 CLOCK SOURCE 34.2 PROGRAMMABLE CLOCK DIVIDER 34.3 SELECTABLE DUTY CYCLE 34.4 OPERATION IN SLEEP MODE FIGURE 34-1: Clock Reference Block Diagram FIGURE 34-2: Clock Reference Timing Register 34-1: CLKRCON: Reference Clock Control Register Register 34-2: CLKRCLK: Clock Reference Clock Selection Register TABLE 34-1: Summary of Registers Associated with Clock Reference Output 35.0 In-Circuit Serial Programming™ (ICSP™) 35.1 High-Voltage Programming Entry Mode 35.2 Low-Voltage Programming Entry Mode 35.3 Common Programming Interfaces FIGURE 35-1: ICD RJ-11 Style Connector Interface FIGURE 35-2: PICkit™ Programmer Style Connector Interface FIGURE 35-3: Typical Connection for ICSP™ Programming 36.0 Instruction Set Summary 36.1 Read-Modify-Write Operations TABLE 36-1: Opcode Field Descriptions TABLE 36-2: Abbreviation Descriptions 36.2 General Format for Instructions TABLE 36-3: Instruction Set TABLE 36-3: Instruction Set (Continued) 36.3 Instruction Descriptions 37.0 Electrical Specifications 37.1 Absolute Maximum Ratings(†) 37.2 Standard Operating Conditions FIGURE 37-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C FIGURE 37-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C 37.3 DC Characteristics TABLE 37-1: Supply Voltage FIGURE 37-3: POR and POR Rearm with Slow Rising Vdd TABLE 37-2: Supply Current (Idd)(1,2,4) TABLE 37-3: Power-Down Current (Ipd)(1,2) TABLE 37-4: I/O Ports TABLE 37-5: Memory Programming Specifications TABLE 37-6: Thermal Characteristics 37.4 AC Characteristics FIGURE 37-4: Load Conditions FIGURE 37-5: Clock Timing TABLE 37-7: External Clock/Oscillator Timing Requirements TABLE 37-8: iNTERNAL Oscillator Parameters(1) FIGURE 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 37-9: PLL Specifications FIGURE 37-7: CLKOUT and I/O Timing TABLE 37-10: I/O and CLKOUT Timing Specifications FIGURE 37-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 37-9: Brown-out Reset Timing and Characteristics TABLE 37-11: Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brown-out Reset Specifications TABLE 37-12: Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2): TABLE 37-13: Analog-to-Digital Converter (ADC) Conversion Timing Specifications FIGURE 37-10: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 37-11: ADC Conversion Timing (ADC Clock from ADCRC) TABLE 37-14: Comparator Specifications TABLE 37-15: 5-Bit DAC Specifications TABLE 37-16: Fixed Voltage Reference (FVR) Specifications TABLE 37-17: Zero Cross Detect (ZCD) Specifications FIGURE 37-12: Timer0 and Timer1 External Clock Timings TABLE 37-18: Timer0 and Timer1 External Clock Requirements FIGURE 37-13: Capture/Compare/PWM Timings (CCP) TABLE 37-19: Capture/Compare/PWM Requirements (CCP) FIGURE 37-14: CLC Propagation Timing TABLE 37-20: Configurable Logic Cell (CLC) Characteristics FIGURE 37-15: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 37-21: EUSART Synchronous Transmission Characteristics FIGURE 37-16: EUSART Synchronous Receive (Master/Slave) Timing TABLE 37-22: EUSART Synchronous Receive Requirements FIGURE 37-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 37-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 37-19: SPI Slave Mode Timing (CKE = 0) FIGURE 37-20: SPI Slave Mode Timing (CKE = 1) TABLE 37-23: SPI Mode requirements FIGURE 37-21: I2C Bus Start/Stop Bits Timing TABLE 37-24: I2C Bus Start/Stop Bits Requirements FIGURE 37-22: I2C Bus Data Timing TABLE 37-25: I2C Bus Data Requirements TABLE 37-26: Temperature Indicator Requirements 38.0 DC and AC Characteristics Graphs and Charts 39.0 Development Support 39.1 MPLAB X Integrated Development Environment Software 39.2 MPLAB XC Compilers 39.3 MPASM Assembler 39.4 MPLINK Object Linker/ MPLIB Object Librarian 39.5 MPLAB Assembler, Linker and Librarian for Various Device Families 39.6 MPLAB X SIM Software Simulator 39.7 MPLAB REAL ICE In-Circuit Emulator System 39.8 MPLAB ICD 3 In-Circuit Debugger System 39.9 PICkit 3 In-Circuit Debugger/ Programmer 39.10 MPLAB PM3 Device Programmer 39.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12 Third-Party Development Tools 40.0 Packaging Information 40.1 Package Marking Information 40.1 Package Marking Information (Continued) TABLE 40-1: 8-Lead 3x3 UDFN Top Marking Appendix A: Data Sheet Revision History Product Identification System The Microchip Website Customer Change Notification Service Customer Support Trademarks Worldwide Sales and Service