link to page 7 link to page 8 link to page 7 link to page 8 IGLD60R190D1600V CoolGaN™ enhancement-mode Power Transistor1Maximum ratings at Tj = 25 °C, unless otherwise specified. Continuous application of maximum ratings can deteriorate transistor lifetime. For further information, contact your local Infineon sales office. Table 3Maximum ratingsParameterSymbolValuesUnitNote/Test ConditionMin. Typ. Max. Drain Source Voltage 1 VDS,max - - 600 V VGS = 0 V Continuous current, drain source ID - - 10 A TC = 25 °C; Pulsed current, drain source 2 3 ID,pulse - - 23 A TC = 25 °C; IG = 9.6 mA; See Figure 3;Figure 5; - - 13.5 A T Pulsed current, drain source 3 4 I C = 125 °C; IG = 9.6 mA; D,pulse See Figure 4;Figure 6; Gate current, continuous 3 4 5 IG,avg - - 7.7 mA Tj = -55 °C to 150 °C; Gate current, pulsed 3 5 IG,pulse - - 770 mA Tj = -55 °C to 150 °C; tPULSE = 50 ns, f=100 kHz Gate source voltage, continuous 5 VGS -10 - - V Tj = -55 °C to 150 °C; Gate source voltage, pulsed 5 VGS,pulse -25 - - V Tj = -55 °C to 150 °C; tPULSE = 50 ns, f = 100 kHz; open drain Power dissipation Ptot - - 62.5 W TC = 25 °C Operating temperature Tj -55 - 150 °C Storage temperature Tstg -55 - 150 °C Max shelf life depends on storage conditions. Drain-source voltage slew-rate dV/dt 200 V/ns 1 All devices are 100% tested at IDS = 4.3 mA to assure VDS ≥ 800 V 2 Limits derived from product characterization, parameter not measured during production 3 Ensure that average gate drive current, IG,avg is ≤ 7.7 mA. Please see figure 27 for IG,avg, IG,pulse and IG details 4 Parameter is influenced by rel-requirements. Please contact the local Infineon Sales Office to get an assessment of your application. 5 We recommend using an advanced driving technique to optimize the device performance. Please see gate drive application note for details. Final Data Sheet 3 Rev. 2.0 2018-11-09 Document Outline Features Benefits Applications Table of Contents 1 Maximum ratings 2 Thermal characteristics 3 Electrical characteristics 4 Electrical characteristics diagrams 5 Test Circuits 6 Package Outlines 7 Appendix A 8 Revision History