Datasheet ALED1262ZT (STMicroelectronics) - 10

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ALED1262ZT Device pin functions 5 Device pin functions
A detailed description about each pin function as follows:
SDA
– I²C is the bidirectional data line, it must be pulled up with an external resistor connected to MCU power supply.
SCL
– clock line, coming from MCU I²C bus, must be pulled up with an external resistor connected to MCU power supply.
CS
– chip-select pin used exclusively to address each device during one time register programming (OTP). This procedure is carried out at the end of customer production line to set the device default configuration. CS pin has an internal pull-down resistor of about 160 kΩ. This pin is also used to supply 15 V during factory programming to set internal OTP registers. Note: The CS pin cannot be connected to GND, neither directly nor through passive components. The only allowed polarization is floating or positive voltage (up to 15 V).
VDDD
– digital power supply coming from MCU section together with I²C bus. When VDDD is below a threshold of about 2.9 V (typ. falling) or 3.0 V (typ. rising) the device goes automatically to SAM. Besides, providing the digital power supply VDDD only (VDDA not connected), the device I²C bus is active and internal registers can be programmed, the only restriction is related to VDDA impedance to GND that must be higher than 4.7 kΩ. In case of a lower impedance, the device digital interface starts on the first VDDA voltage rising edge. The allowed slew rate for this pin is below 0.17 V/µs (0 to 5 V; 30 µs ≤ trise). Note: Fast VDDD edges can cause internal regulator overvoltage spikes that may provoke electrical stresses in the device.
VDDA
– analog power supply coming from car body system. This is the main supply voltage for the driver and it can be dimmed to change LED brightness (100 or 200 Hz at 10% as minimum duty cycle, VDDA = 0 to 12 V). Allowed slew rates for this pin are the following: from 0.4 to 1.2 V/µs (0 to 12 V; 10 µs ≤ trise/fall ≤ 30 µs) in normal operation, from 6.8 to 8.4 V/ms for load dump conditions. Note: If the I²C is programmed to only provide the digital power supply VDDD (VDDA not connected), a subsequent VDDA plug or unplug with edges faster than those allowed (trise/fall < 10 µs) may induce the internal register reset.
LDO3
– internal regulator output pin to be connected to an external capacitor (minimum value 1 µF). The output voltage is about 3.3 V ±3% and it is used as an external reference voltage and the device internal supply. The capacitor connected on this pin is also used as “tank capacitor” to maintain internal volatile register data during VDDA pulsed dimming function (if required).
REXT
– this resistor is used to program the regulated output current. The relationship between REXT value and the output current is given by the following equation: V I BG Ox = R ∙ K EXT The current gain factor "K" is about 240. The VBG voltage is normally at 1.233 V used to get the reference current trough R-EXT pin; this current is mirrored by a precise circuit to generate the reference for the driver stage. On R- EXT pin, any filter capacitor can be connected.
GND
– ground pin, it must be connected to a package exposed pad. Exposed pad should be soldered directly to the PCB to see the thermal benefits (see the device thermal management section).
GPWM
– a variable duty cycle square wave on this pin allows all channels brightness to be fixed simultaneously (PWM global dimming). If this pin is not used, it must be connected to LDO3. GPWM control requires a square wave with a HIGH level longer than 20 µs caused by a 15 µs delay needed to power on all internal blocks before the channel activation. With 20 µs HIGH level, the real output activation is around 5 µs. The maximum allowed slew-rate on this pin is 1.9 V/µs.
OUTx
– the ALED1262ZT has 12 current regulated low-side outputs. The output stage is a sinker, which is able to stand till 19 V, this is to use more than one LED series connected. The internal current generator turn-on and turn- off time has been slowed down to decrease as much as possible EMI noise.
FLG
– this is the fault flag I/O pin used in wired-OR among those devices sharing the same application. In wired- OR connection, all FLG pins are connected together to a single pull-down resistor, this signal can also be read by an MCU to detect any fault condition. If the device receives an external error status, it reacts according to the internal configuration (see Section 13.1 BDM_conf_1 / Enable_CH_1 register, Section 13.2 BDM_conf_2 /
DS12631
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Rev 4 page 10/69
Document Outline 1 Pin description 2 Absolute maximum ratings 3 Thermal characteristics 4 Electrical characteristics 4.1 Switching characteristics 5 Device pin functions 6 Driver dropout voltage 7 Device functional description 8 Error detection 9 Gradual output delay 10 Thermal warning and protection 11 Device local dimming function 12 Local dimming non-linear step table 13 Register descriptions 13.1 BDM_conf_1 / Enable_CH_1 register 13.2 BDM_conf_2 / Enable_CH_2 register 13.3 BDM_status register 13.4 Faulty_ch_1 register 13.5 Faulty_ch_2 register 13.6 PWM_gain_x register 13.7 LDD register (LED driver device versioning) 13.8 OTP/SAM_conf_1_2 register 13.9 OTP/SAM_conf_1 register 13.10 OTP/SAM_conf_2 register 13.11 OTP/BA_n_SAM_setting register 14 I²C bus operations 14.1 I²C main concepts 15 I²C addressing for the ALED1262ZT 16 I²C selectable Hamming (8, 4) encoding 17 Message structure 17.1 Available commands 17.2 Pattern symbols 17.3 Write operations 17.3.1 BDM configuration register write 17.3.2 FAULTY_ch1[7] bit register write (prescaler) 17.3.3 PWM_gain_x register write 17.3.4 BDM_conf and PWM_gain_x register write 17.3.5 Direct write on registers 17.4 Read operations 17.4.1 Status register 17.4.2 Faulty_ch registers 17.4.3 PWM_gain_x registers 17.4.4 BDM_conf, status, Faulty_ch, PWM_gain_x registers 17.4.5 Direct read from registers 18 OTP operations 18.1 OTP emulate 18.2 OTP burn 18.3 OTP read 19 I²C communication examples 19.1 Communication without parity detection 19.1.1 OTP burning with double zap and read back 19.1.2 All LEDs with power-ON 19.1.3 110 Hz dimming prescaler bit 19.1.4 All LEDs with PWM dimming at 50% (full configuration) 19.1.5 Device status read back 19.1.6 Device full status read back 19.1.7 LDD read back (device identifier) 19.2 Communication with parity detection 19.2.1 All LEDs with power-ON 20 LED supply voltage 21 Higher current requests (outputs in parallel) 22 PCB layout and external component guidelines 22.1 Signal integrity and EMI radiated/conducted immunity 22.2 Radiated emission reduction (EMI) 22.3 Device thermal management 22.4 PCB layout example 23 Package information 23.1 HTSSOP24 exposed pad package information Revision history