Datasheet IS2083 (Microchip) - 9

IS2083 Device Overview 2. Device Overview
The IS2083BM uses a single-cycle 8-bit 8051 MCU core connected to the system components via an MCU system bus. The MCU system bus provides interface memory map address decode for the Read Only Memory (ROM), Static Random Access Memory (SRAM), and peripherals. IS2083BM contains the following major blocks: • Bluetooth Link Controller (BTLC) – Bluetooth clock, task scheduler, and Bluetooth hopping • Bluetooth modulator-demodulator (modem) – TX/RX baseband, and RF • DSP audio subsystem – DSP with audio codec • Program ROM Memory • Bluetooth DMA – Common Memory Access • Power Management Unit (PMU) • Clock/Reset – Low power logic
Figure 2-1. IS2083BM SoC Architecture CPU Subsystem To Memories Interrupt Controller Program ROM Debug OCI Patch 2 MB 8-bit 8051 MMU WDT I2C PWM GPIO SQI Host Debug CPU Core Logic Flash Patch RAM CPU Program/Data Bus Mailbox Baseband
IO Bus
DSP Subsystem Hopping Bluetooth Task Bluetooth Sequence Clock DSP Core Controller Baseband Core Controller Timer DMA External Codec RF SPORT0 Controller Program Data RAM RAM CLDO RFLDO Coeff. Patch
TX path
Controller RAM RAM
+
Memory Bluetooth 5.0
TX modem IO Bus
Dual Mode Radio
RX path +
Audio MIC
RX modem
Stereo 288 MHz XTAL ULPC BG Subsystem Audio Codec PLL SPK
16 MHz
UART RS-232
32 kHz
CLKGEN Common
0-48 MHz
Memory USB USB
0-96 MHz The IS2083BM device variants are: • IS2083BM variant supports analog output from the internal DAC • IS2083BM-2L2 variant supports LDAC and does not support analog output The following table provides the features of IS2083BM SoC variants. © 2019 Microchip Technology Inc.
Datasheet
DS70005403B-page 9 Document Outline Introduction Features Table of Contents 1. Quick References 1.1. Reference Documentation 1.2. Acronyms/Abbreviations 2. Device Overview 2.1. IS2083BM Device Ball Diagram 2.2. IS2083BM Device Ball Description 3. Audio Subsystem 3.1. Digital Signal Processor 3.2. Codec 3.2.1. Audio Performance 3.3. Auxiliary Port 3.4. Microphone Inputs 3.5. Analog Speaker Output 4. Bluetooth Transceiver 4.1. Transmitter 4.2. Receiver 4.3. Synthesizer 4.4. Modulator-Demodulator 4.5. Adaptive Frequency Hopping 5. Microcontroller 5.1. Memory 5.2. Clock 6. Power Management Unit 6.1. Device Operation 6.2. Power Supply 6.3. Adapter Input 6.4. Buck1 (BK1) Switching Regulator 6.5. Buck2 (BK2) Switching Regulator 6.6. Low-Droput Regulator 6.7. Battery Charging 6.7.1. Battery Charger Detection 6.8. SAR ADC 6.9. LED Driver 7. Application Information 7.1. Power On/Off Sequence 7.2. Reset 7.3. Programming and Debugging 7.3.1. Test Mode 7.3.2. Flash Memory and SQI Controller 7.3.2.1. SQI Controller 7.3.3. 2-wire Interface 7.3.3.1. Serial Program Clock 7.3.3.2. Serial Program Data 7.3.4. Enabling Programming Interface 7.3.5. On-chip Instrumentation 7.3.5.1. Enabling OCI Functionality 7.3.5.2. Entering Debug Mode 7.3.5.3. Reading the Debug Status 7.3.5.4. Reading the Program Counter 7.3.5.5. Stopping Program Execution (Entering Debug Mode) 7.3.5.6. Starting Program Execution (Exiting Debug Mode) 7.3.5.7. User Single Step Mode 7.3.5.8. OCI Single Step Mode 7.3.5.9. Setting Software Breakpoints 7.3.5.10. Simple and Complex Debug Triggers 7.3.5.11. Reading and Writing Memory/SFR Registers 7.3.5.12. Trace Buffer 7.3.5.13. Instruction Trace 7.4. General Purpose I/O Pins 7.5. I2S Mode Application 7.6. Host MCU Interface 8. Electrical Specifications 8.1. Timing Specifications 9. Package Information 10. Ordering Information 11. Document Revision History The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service