Datasheet AD7711A (Analog Devices) - 10

AD7711A PGA GAIN G2 Gl G0 Gain
0 0 0 1 (Default Condition after the Internal Power-On Reset) 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
Channel Selection CH Channel
0 AIN1 (Default Condition after the Internal Power-On Reset) 1 AIN2
Power-Down PD
0 Normal Operation (Default Condition after the Internal Power-On Reset) 1 Power-Down
Word Length WL Output Word Length
0 16-Bit (Default Condition after Internal Power-On Reset) 1 24-Bit
RTD Excitation Current IO
0 Off (Default Condition after Internal Power-On Reset) 1 On
Burnout Current BO
0 Off (Default Condition after Internal Power-On Reset) 1 On
Bipolar/Unipolar Selection (Both Inputs) B/U
0 Bipolar (Default Condition after Internal Power-On Reset) 1 Unipolar
Filter Selection (FS11–FS0)
time) for the device is equal to the frequency selected for the The on-chip digital filter provides a sinc3 (or (sinx/x)3) filter first notch of the filter. For example, if the first notch of the response. The 12 bits of data programmed into these bits deter- filter is selected at 50 Hz, then a new word is available at a 50 Hz mine the filter cutoff frequency, the position of the first notch of rate or every 20 ms. If the first notch is at 1 kHz, a new word is the filter, and the data rate for the part. In association with the available every 1 ms. gain selection, it also determines the output noise (and therefore The settling time of the filter to a full-scale step input change is the effective resolution) of the device. worst case 4 ¥ 1/(output data rate). This settling time is to The first notch of the filter occurs at a frequency determined by 100% of the final value. For example, with the first filter notch the relationship filter first notch frequency = (f at 50 Hz, the settling time of the filter to a full-scale step input CLK IN/512)/code where code is the decimal equivalent of the code in bits FS0 to change is 80 ms max. If the first notch is at 1 kHz, the settling FS11 and is in the range 19 to 2,000. With the nominal f time of the filter to a full-scale input step is 4 ms max. This CLK IN of 10 MHz, this results in a first notch frequency range from settling time can be reduced to 3 ¥ l/(output data rate) by syn- 9.76 Hz to 1.028 kHz. To ensure correct operation of the chronizing the step input change to a reset of the digital filter. In AD7711A, the value of the code loaded to these bits must be other words, if the step input takes place with SYNC low, the within this range. Failure to do this will result in unspecified settling time will be 3 ¥ l/(output data rate). If a change of chan- operation of the device. nels takes place, the settling time is 3 ¥ l/(output data rate), regardless of the SYNC input. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect The –3 dB frequency is determined by the programmed first of the filter notch frequency and gain on the effective resolution notch frequency according to the relationship filter –3 dB of the AD7711A. The output data rate (or effective conversion frequency = 0.262 ¥ first notch frequency. –10– REV. D