Datasheet TB67S158NG (Toshiba) - 10

TB67S158NG
7. Pin function of serial/parallel conversion control I/F (Mode2) 7-1. Input interface (8bit shift register + 8bit storage register) CLK DATA 8bit shift register CLR Qa Qb Qc Qd Qe Qf Qg Qh 8bit storage register LATCH QA QB QC QD QE QF QG QH GATE Logic input gate - - - - A+ A B+ B C+ C D+ D _ _ _ _ _ _ _ _ E E E E E E E E NABL NABL NABL NABL NABL NABL NABL NABL E E E E E E E E STBY Motor Control Logic * Initial value for each logic pin when signal is not inputted
Pin name Initial value CLK Low DATA Low CLR Low LATCH Low GATE High STBY Low Initial state for each logic pin when signal is not inputted is as follows. LATCH: Low=sift register/storage register: initial state GATE: High=ENABLE_X+,ENABLE_X-=Disable * ”X” of ENABLE_X stands for A, B, C, and D. STBY=Low: standby state 10 2015-5-11