Datasheet LYTSwitch-6 (Power Integrations) - 6

LYTSwitch-6
As an additional safety measure the primary will pause for an The secondary control er temporarily inhibits the FEEDBACK short auto-restart on-time, t (~82 ms), before switching. During this protection threshold (V ) until the end of the soft-start (t ) AR FB(OFF) SS(RAMP) “wait” time, the primary will “listen” for secondary requests. If it sees timer. After hand-shake is completed the secondary control er two consecutive secondary requests, separated by 30 ms, the primary linearly ramps up the switching frequency from f to f over the SW SREQ will enter secondary control and begins switching in slave mode. If t time period. SS(RAMP) no such pulses occur during the t “wait” period, the primary will AR begin switching under primary control until handshake pulses are In the event of a short-circuit or overload at start-up, the device will received. regulate directly into CC (constant-current mode). The device will go into auto-restart (AR), if the output voltage does not rise above the
Audible Noise Reduction Engine
V threshold before the expiration of the V AR timer (t ) after The LYTSwitch-6 features and active audible noise reduction mode O(AR) OUT FB(AR) handshake has occurred. wherein the control er (via a “frequency skipping” mode of operation) avoids the resonant band (where the mechanical structure of the The secondary control er enables the FEEDBACK pin short protection power supply is most likely to resonate ‒ increasing noise amplitude) mode (V ) at the end of the t time period. If the output FB(OFF) SS(RAMP) between 5 kHz and 12 kHz ‒ 200 ms and 83 ms period respectively. If a short maintains the FEEDBACK pin to be below short-circuit threshold secondary control er request occur within this window from the last the secondary will stop requesting pulses to trigger an auto-restart conduction cycle, the gate drive of the power switch is inhibited. cycle.
Secondary Controller
If output voltage reaches regulation within the t time period, SS(RAMP) the frequency ramp is immediately aborted and the secondary As shown in the block diagram in Figure 4, the IC is powered through control er is permitted to go full frequency. This will al ow the regulator 4.4 V (V ) by either VOUT or FW. The SECONDARY BPS control er to maintain regulation in the event of a sudden transient BYPASS pin is connected to an external decoupling capacitor and fed loading soon after regulation is achieved. The frequency ramp will internal y from the regulator block. only be aborted if quasi-resonant detection programming has already The FORWARD pin also connects to the negative edge detection occurred. block used for both handshaking and timing to turn on the SF FET
Maximum Secondary Inhibit Period
connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The Secondary-cycle requests to initiate primary switching are inhibited to FORWARD pin voltage is used to determine when to turn off the maintain operation below maximum frequency and ensure minimum SF FET in discontinuous mode operation. This is when the voltage off-time. Besides these constraints, secondary-cycle requests are across the R of the SR FET drops below zero volts. DS(ON) also inhibited during the “ON” time cycle of the primary switch (time In continuous conduction mode (CCM) the SR FET is turned off when between the cycle request and detection of FORWARD pin falling the feedback pulse is sent to the primary to demand the next edge). The maximum time-out in the event a FORWARD pin falling switching cycle, providing excel ent synchronous operation, free of edge is not detected after a cycle requested is ~30 ms. the any overlap for the FET turn-off.
Thermal Foldback
When the secondary control er die temperature reaches 124 °C, the The mid-point of an external resistor divider network between the output power is reduced by reducing the constant current reference OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the threshold (see Figure 8). FEEDBACK pin to regulate the output voltage. The internal voltage comparator reference voltage is V (1.265 V). REF The external current sense resistor connected between ISENSE and SECONDARY GROUND pins to regulate the output current in constant current regulator mode. 100
Minimum Off-Time
The secondary control er initiates cycle request using the inductive connection to the primary. The maximum frequency of the secondary-cycle requests is limited by a minimum cycle off-time of t . This is in order to ensure that there is sufficient reset time 70 OFF(MIN) after the primary conduction to deliver energy to the load.
Maximum Switching Frequency
The maximum switch request frequency of the secondary control er is f .
Maximum Output Current (%)
SREQ 109 124
Frequency Soft-Start Secondary Controller Die
At start-up the primary control er is limited to a maximum switching
Temperature (ºC)
frequency of f and 75% of the maximum programmed current limit SW at the switch-request frequency of 100 kHz. PI-8376b-080619 Figure 8. Maximum Output Current vs. Secondary Die Temperature.
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Rev. G 08/19 www.power.com Document Outline Product Highlights Description Output Power Table LYTSwitch-6 Functional Description Primary Controller Secondary Controller Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing MSL Table ESD and Latch-Up Table Part Ordering Information