Datasheet TPS7A02 (Texas Instruments) - 10

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TPS7A02
SBVS277 – JULY 2019
www.ti.com 7.3 Feature Description 7.3.1 Excellent Transient Response
The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the device response time to transients. Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the loop. The device response time across the output voltage range is constant because a buffered reference topology is used, which keeps the control loop in unity gain at any output voltage. These features give the device a wide loop bandwidth during transients that ensures excellent transient response while maintaining the device low IQ in steady-state conditions.
7.3.2 Active Discharge (P-Version Only)
The device has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by the undervoltage lockout (UVLO).
ADV
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
ANCEINFORMA
short period of time.
7.3.3 Low IQ in Dropout
In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for low IQ LDOs with adaptive biasing. The TPS7A02 detects when operating in dropout conditions and disables the adaptive biasing, thus minimizing the IQ increase.
7.3.4 Smart Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the enable pin to the input of the device.
TION
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical Characteristics table. This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the output voltage.
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device. V R = DO DS(ON) IRATED (1) 10 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Switching Characteristics 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Excellent Transient Response 7.3.2 Active Discharge (P-Version Only) 7.3.3 Low IQ in Dropout 7.3.4 Smart Enable 7.3.5 Dropout Voltage 7.3.6 Foldback Current Limit 7.3.7 Undervoltage Lockout (UVLO) 7.3.8 Thermal Shutdown 7.4 Device Functional Modes 7.4.1 Device Functional Mode Comparison 7.4.2 Normal Operation 7.4.3 Dropout Operation 7.4.4 Disabled 8 Application and Implementation 8.1 Application Information 8.1.1 Recommended Capacitor Types 8.1.2 Input and Output Capacitor Requirements 8.1.3 Load Transient Response 8.1.4 Undervoltage Lockout (UVLO) Operation 8.1.5 Power Dissipation (PD) 8.1.5.1 Estimating Junction Temperature 8.1.5.2 Recommended Area for Continuous Operation 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Examples 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information