Datasheet ADN2890 (Analog Devices) - 8

ADN2890 Data Sheet THEORY OF OPERATION LIMAMP RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) Input Buffer
The ADN2890 has an on-chip RSSI circuit that automatical y The limiting amplifier has differential inputs (PIN/NIN), with detects the average received power based on a direct measure- an internal 50 Ω termination. The ROSA (receive optical sub- ment of the PIN photodiode’s current. The photodiode bias is assembly) is typically ac-coupled to the ADN2890 inputs, supplied by the ADN2890, which allows a very accurate, on- although dc coupling is possible. chip, average power measurement based on the amount of current supplied to the photodiode. The output of the RSSI is a An internal offset correction loop requires that a capacitor be current that is directly proportional to the average amount of connected between the CAZ1 and CAZ2 pins. A 0.01 µF PIN photodiode current. Placing a resistor between the capacitor provides a low frequency cutoff of 2 kHz. RSSI_OUT pin and GND converts the current to a GND
CML Output Buffer
referenced voltage. This function eliminates the need for The ADN2890 provides CML outputs, OUTP/OUTN. The external RSSI circuitry in SFF-8472 compliant optical receivers. outputs are internal y terminated with 50 Ω to VCC.
SQUELCH MODE
The outputs can be kept at a static voltage by driving the Driving the SQUELCH input to a logic high disables the SQUELCH pin to a logic high. The SQUELCH pin can be limiting amplifier outputs. The SQUELCH input can be driven directly by the LOS pin, which automatically disables connected to the LOS output to keep the limiting amplifier the LIMAMP outputs in situations with no data input. outputs at a static voltage level anytime the input level to the
LOSS OF SIGNAL (LOS) DETECTOR
limiting amplifier drops below the programmed LOS threshold. The receiver front-end LOS detector circuit indicates when the input signal level has fallen below the user-adjustable threshold. The threshold is set by a resistor connected between the THRADJ pin and V EE. The ADN2890 LOS circuit has a trip point down to <3.0 mV with >3 dB electrical hysteresis to prevent chatter at the LOS output. The LOS output is an open- col ector output that must be pul ed up externally with a 4.7 kΩ to 10 kΩ resistor. Rev. B | Page 8 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMAMP Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes PCB Layout Soldering Guidelines for Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE NOTES