Datasheet MP28300 (Monolithic Power Systems) - 5
| Fabricante | Monolithic Power Systems |
| Descripción | 300mA, 5.5V, 500nA, Ultra-Low Iq, Synchronous, Step-Down Converter plus 100mA LDO in 2x2 QFN |
| Páginas / Página | 20 / 5 — MP28300 – ULTRA-LOW IQ STEP-DOWN CONVERTER. ELECTRICAL CHARACTERISTICS … |
| Formato / tamaño de archivo | PDF / 657 Kb |
| Idioma del documento | Inglés |
MP28300 – ULTRA-LOW IQ STEP-DOWN CONVERTER. ELECTRICAL CHARACTERISTICS (continued)
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MP28300 – ULTRA-LOW IQ STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS (continued) VIN1 = 3.6V, VIN2 = 3.6V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C. The limit over temperature is guaranteed by characterization, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units LDO Section
No load, CTRL1/2/3 = 0V, Supply current (quiescent) IQ_LDO CTRL4/5 = L/H, 300 nA no load current from VIN2 Supply current (shutdown) ISD_25 CTRL4/5 = 0V, or EN = 0 50 nA Voltage dropout of LDO VDP ILDO = 0.1A, VOUT = 3.3V 50 mV Dropout resistance RDP 0.5 Ω Current limit of LDO ILIM_LDO 150 200 mA CTRL4/5 = L/H, TJ = 25°C, 1.782 1.800 1.818 CTRL4/5 DC output voltage accuracy V = L/H, TJ = -40°C to 85°C 1.773 1.827 OUT V Internal reference, 0.591 0.600 0.609 TA = -40°C to 85°C Line regulation of LDO IOUT = 1mA 0 % Load regulation of LDO IOUT = 1mA to 100mA -1 1 % 10Hz, IOUT = 100mA 40 Power supply rejection ratio (6) PSRR 100Hz, IOUT = 100mA 20 dB 1kHz, IOUT = 100mA 15
Both Buck and LDO
TSS Buck 0.5 ms Internal soft-start time LDO: V T OUT = 3.3V, IOUT = 100mA, SS 2 ms Co = 1µF Discharge resistance during R enable off DIS_OFF 50 Ω CTRL high logic CTRLH 1.2 V CTRL low logic CTRLL 0.4 V VCTRL = 3.6V 1 CTRL input current ICTRL VCTRL = 0 0 nA VEN = 0V 0 CTRL turn-on delay TD 300 μs Not present when CTRL is high CTRL pull-down resistor RPD 2 MΩ to avoid IQ impact Power good threshold PG FB with respect to the regulation 90 % Power good hysteresis PGHys 10 % Power good delay PGTD 75 μs Power good sink current V capability PG_LO Sink 1mA 0.4 V Power good leakage current IPGLK VPGBUS = 1.8V 10 nA Thermal shutdown (5) TSD 150 °C Thermal hysteresis (5) TSDHY 30 °C
NOTES:
5) Guaranteed by design. 6) Data derived from bench characterization test. MP28300 Rev.1.1 www.MonolithicPower.com 5 6/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.
No load, CTRL1/2/3 = 0V, Supply current (quiescent) IQ_LDO CTRL4/5 = L/H, 300 nA no load current from VIN2 Supply current (shutdown) ISD_25 CTRL4/5 = 0V, or EN = 0 50 nA Voltage dropout of LDO VDP ILDO = 0.1A, VOUT = 3.3V 50 mV Dropout resistance RDP 0.5 Ω Current limit of LDO ILIM_LDO 150 200 mA CTRL4/5 = L/H, TJ = 25°C, 1.782 1.800 1.818 CTRL4/5 DC output voltage accuracy V = L/H, TJ = -40°C to 85°C 1.773 1.827 OUT V Internal reference, 0.591 0.600 0.609 TA = -40°C to 85°C Line regulation of LDO IOUT = 1mA 0 % Load regulation of LDO IOUT = 1mA to 100mA -1 1 % 10Hz, IOUT = 100mA 40 Power supply rejection ratio (6) PSRR 100Hz, IOUT = 100mA 20 dB 1kHz, IOUT = 100mA 15
Both Buck and LDO
TSS Buck 0.5 ms Internal soft-start time LDO: V T OUT = 3.3V, IOUT = 100mA, SS 2 ms Co = 1µF Discharge resistance during R enable off DIS_OFF 50 Ω CTRL high logic CTRLH 1.2 V CTRL low logic CTRLL 0.4 V VCTRL = 3.6V 1 CTRL input current ICTRL VCTRL = 0 0 nA VEN = 0V 0 CTRL turn-on delay TD 300 μs Not present when CTRL is high CTRL pull-down resistor RPD 2 MΩ to avoid IQ impact Power good threshold PG FB with respect to the regulation 90 % Power good hysteresis PGHys 10 % Power good delay PGTD 75 μs Power good sink current V capability PG_LO Sink 1mA 0.4 V Power good leakage current IPGLK VPGBUS = 1.8V 10 nA Thermal shutdown (5) TSD 150 °C Thermal hysteresis (5) TSDHY 30 °C
NOTES:
5) Guaranteed by design. 6) Data derived from bench characterization test. MP28300 Rev.1.1 www.MonolithicPower.com 5 6/12/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.