Datasheet LTC3622, LTC3622-2, LTC3622-23/5 (Analog Devices) - 9

link to page 1 link to page 13 link to page 13 LTC3622/ LTC3622-2/LTC3622-23/5
PIN FUNCTIONS (DFN/MSOP) VIN1 (Pin 1/Pin 1):
Input Voltage of Channel 1 Step-Down
RUN2 (Pin 9/Pin 10):
Logic Controlled RUN Input to Chan- Regulator. This input also powers the INTVCC LDO. nel 2. Do not leave this pin floating. Logic high activates
PGOOD1 (Pin 2/Pin 3):
Open Drain Power Good Indicator the step-down regulator. for Channel 1.
FB2 (Pin 10/Pin 11):
Feedback Input to the Error Amplifier
MODE/SYNC (Pin 3/Pin 4):
Burst Mode Select and External of Channel 2 Step-Down Regulator. Connect resistor divider Clock Synchronization of the Step-Down Regulator. Tie tap to this pin. The output voltage can be adjusted from MODE/SYNC to INTV 0.6V to VIN by: VOUT = 0.6V • [1 + (R2/R1)]. (Figure 2) For CC for Burst Mode operation with a 400mA peak current clamp. Tie MODE/SYNC to GND for fixed VOUT options, connect the FB pin directly to VOUT. pulse-skipping operation. Furthermore, connecting this pin
INTVCC (Pin 11/Pin 12):
Low Dropout Regulator. Bypass to an external clock will synchronize the switch clock to with a low ESR capacitor of at least 1µF to ground. the external clock and put the part in pulse-skipping mode.
FB1 (Pin 12/Pin 13):
Feedback Input to the Error Amplifier
PHASE (Pin 4/Pin 5):
Phase Select Pin. Tie this pin to of Channel 1 Step-Down Regulator. Connect resistor divider ground to run the regulators in phase (0° phase shift) tap to this pin. The output voltage can be adjusted from between SW rising edge of channel 1 and channel 2. Tie 0.6V to VIN by: VOUT = 0.6V • [1 + (R2/R1)]. (Figure 2) For this pin to INTVCC to set 180° phase shift between chan- fixed VOUT options, connect the FB pin directly to VOUT. nels. When this pin is high, the phase shift may also be
RUN1 (Pin 13/Pin 14):
Logic Controlled RUN Input to set by modulating the duty cycle of external clock on the Channel 1. Do not leave this pin floating. Logic high acti- MODE/SYNC pin (channel 1 edge synced to rising edge vates the step-down regulator. of external clock, channel 2 edge synced to falling edge of external clock). See Applications section for more details.
SW1 (Pin 14/Pin 16):
Switch Node Connection to the Inductor of Channel 1 Step-Down Regulator.
PGOOD2 (Pin 5/Pin 6):
Open Drain Power Good Indicator for Channel 2.
GND (Pin 15/Pin 17):
Ground for Power and Signal Ground. The exposed pad must be connected to PCB ground for
ILIM (Pin 6/Pin 7):
Current Limit Select Pin. Tying this pin rated electrical and rated thermal performance. to ground sets the full current limit for both channels. Tying this pin to INTVCC drops the current limit by a factor of 2
SVIN (NA/Pin 2):
Signal VIN Pin. This input powers the for both channels. Biasing this pin to 1V sets the current INTVCC. May be a different voltage than either VIN1 or on channel 1 to be the full amount, and the current on VIN2. Connect SVIN to either VIN1 or VIN2 , whichever one channel 2 to be dropped by a factor of 2. is higher. For applications where it is not known which VIN is higher, connect external diode between SV
VIN2 (Pin 7/Pin 8):
Input Voltage of Channel 2 Step-Down IN to both VIN1 and V Regulator. May be a different voltage than V IN2 to ensure that SVIN is less than a diode drop from IN1. the higher of VIN1 or VIN2.
SW2 (Pin 8/Pin 9):
Switch Node Connection to the Induc- tor of Channel 2 Step-Down Regulator. Rev D For more information www.analog.com 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts