Datasheet LTC7103 (Analog Devices) - 9

link to page 18 LTC7103
PIN FUNCTIONS RUN (Pin 3):
Run Control Input. Holding this pin below the LTC7103 operates in pulse-skipping mode. When not 1.1V shuts off the switching regulator. Holding this pin synchronizing to an external clock, this input determines below 0.7V reduces the quiescent current to approxi- how the LTC7103 operates at light loads. Tie this pin to mately 0.7µA. Place a resistor divider between VIN and SGND or float to select Burst Mode operation or tie this this pin to use as an undervoltage lockout. Tie this pin to pin to INTVCC through a 100k resistor to select pulse- VIN to always enable the LTC7103. skipping operation. This pin sinks 10µA to SGND. Do not
SGND (Pin 6):
Signal Ground. tie this pin directly to INTVCC.
OVLO (Pin 7):
Overvoltage Shutdown Input. If the voltage
CLKOUT (Pin 13):
Output clock signal available to syn- on this pin exceeds 1.21V, then the switching regulator chronize additional regulators for parallel operation. The is shut down and the SS pin is internally grounded. Tie rising edge of CLKOUT is 180° out of phase with respect this pin to SGND to allow operation with V to the rising edge of the SW pin. The output level swings IN up to 105V. from SGND to INTVCC.
RIND (Pin 8):
Sets the current used to create an internal ramp that replicates the inductor current up-slope for low
PGOOD (Pin 14):
Open-Drain Power Good Output. The duty cycle operation. This pin generates a voltage that VFB pin is monitored to ensure that the output is in regu- varies with the switching frequency. Place a resistor to lation. When the output is not in regulation, the PGOOD SGND on this pin equal to 1/(7.5 • L) to set the internal pin is pulled low. ramp current. This pin can be left floating if fixed output
SS (Pin 15):
Soft-Start and Regulator Timeout Input. The voltage mode is selected using the VPRG1 and VPRG2 pins. voltage on the SS pin limits the regulated output voltage If VPRG1 and VPRG2 are both floating, then a resistor from when the SS voltage is less than 1V. An internal 10μA RIND to SGND must be used. pull-up current source is connected to this pin. A capaci-
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tor to ground at this pin sets the ramp time to final regu-
TH (Pin 9):
Error Amplifier Output and Switching Regulator Compensation Point. Place compensation lated output voltage. Leave this pin floating to use the components between the I internal 1.2ms soft-start ramp. The SS pin also serves TH pin and SGND. Tie this pin to INTV as a timeout to disable switching if the EXTVCC voltage CC for fixed internal compensation. is too low. To disable the regulator timeout feature, tie a
VFB (Pin 10):
Regulator Feedback Input. When set to 75k resistor between SS and INTVCC. See Soft-Start and adjustable mode, use an external resistor divider between LDO Regulator Timeout in the Applications Information the regulator output voltage and the VFB pin. For fixed out- section. put voltage mode, tie VFB directly to the regulator output.
ICTRL (Pin 16):
Programs the Average Output Current in
FREQ (Pin 11):
The frequency control pin for the internal Constant Current Mode. The voltage on this pin deter- VCO. Connect this pin to SGND for 300kHz operation or mines the maximum ITH voltage, which in turn sets the to INTVCC for 1MHz operation. Place a resistor to SGND average output current in constant-current mode. The on this pin to set the operating frequency between 200kHz peak current limit tracks 1.2A above the average current and 2MHz. Minimize the capacitance on this pin if Burst limit set point. Tie this pin to a voltage between 0.4V and Mode operation is used. This pin sources 40µA. 1.3V to program the average output current to a value
PLLIN/MODE (Pin 12):
External Synchronization Input between 0A and 2.5A. An internal 20μA pull-up on this to Phase Detector and Burst Mode Control Input. When pin allows a single resistor to SGND to be used to set the an external clock is applied to this pin, the phase-locked voltage. Float this pin to set the average output current to loop will force the rising edge of the SW signal to be syn- 2.5A and the peak current limit to 3.7A. chronized with the rising edge of the external clock, and Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts