Datasheet LTC3863 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 60V Low IQ Inverting DC/DC Controller |
| Páginas / Página | 38 / 9 — PIN FUNCTIONS GATE (Pin 12):. PGND (Exposed Pad Pin 13):. FUNCTIONAL … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 1.5 Mb |
| Idioma del documento | Inglés |
PIN FUNCTIONS GATE (Pin 12):. PGND (Exposed Pad Pin 13):. FUNCTIONAL DIAGRAM
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LTC3863
PIN FUNCTIONS GATE (Pin 12):
Gate Drive Output for External P-Channel
PGND (Exposed Pad Pin 13):
Ground Reference for Power MOSFET. The gate driver bias supply voltage (VIN-VCAP) Components (Power Ground). The PGND exposed pad must is regulated to 8V when VIN is greater than 8V. The gate be soldered to the circuit board for electrical contact and driver is disabled when (VIN-VCAP) is less than 3.5V (typi- for rated thermal performance of the package. Connect cal), 3.8V maximum in start-up and 3.25V (typical) 3.5V signal ground to power ground only at one point using a maximum in normal operation. single PCB trace.
FUNCTIONAL DIAGRAM
VIN UVLO V CIN IN + 3.25V – RSENSE SENSE 0.4µA RUN RUN + – 1.26V – LOGIC GATE CONTROL DRV MP D1 Q S R VOUT IN CCAP Burst Mode COUT OPERATION LDO L CLOCK PLLIN/MODE + O.425V OUT MODE/CLOCK DETECT PLL V CAP IN – 8V SYSTEM – ICMP 20µA VCO – + FREQ RFREQ + 10µA SS SGND + + 0.8V SLOPE CSS COMPENSATION – 0.5µA EN EA RFB1 OV + 0.88V – (G VFBN m = 1.8mS) – + R C FB2 FB2 VFB PGND ITH 3863 FD RITH CITH1 Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS GATE (Pin 12):
Gate Drive Output for External P-Channel
PGND (Exposed Pad Pin 13):
Ground Reference for Power MOSFET. The gate driver bias supply voltage (VIN-VCAP) Components (Power Ground). The PGND exposed pad must is regulated to 8V when VIN is greater than 8V. The gate be soldered to the circuit board for electrical contact and driver is disabled when (VIN-VCAP) is less than 3.5V (typi- for rated thermal performance of the package. Connect cal), 3.8V maximum in start-up and 3.25V (typical) 3.5V signal ground to power ground only at one point using a maximum in normal operation. single PCB trace.
FUNCTIONAL DIAGRAM
VIN UVLO V CIN IN + 3.25V – RSENSE SENSE 0.4µA RUN RUN + – 1.26V – LOGIC GATE CONTROL DRV MP D1 Q S R VOUT IN CCAP Burst Mode COUT OPERATION LDO L CLOCK PLLIN/MODE + O.425V OUT MODE/CLOCK DETECT PLL V CAP IN – 8V SYSTEM – ICMP 20µA VCO – + FREQ RFREQ + 10µA SS SGND + + 0.8V SLOPE CSS COMPENSATION – 0.5µA EN EA RFB1 OV + 0.88V – (G VFBN m = 1.8mS) – + R C FB2 FB2 VFB PGND ITH 3863 FD RITH CITH1 Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts