Datasheet ADP5071 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| Páginas / Página | 27 / 5 — Data Sheet. ADP5071. ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL … |
| Revisión | E |
| Formato / tamaño de archivo | PDF / 1.0 Mb |
| Idioma del documento | Inglés |
Data Sheet. ADP5071. ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE. Parameter. Rating. Table 4. Thermal Resistance
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Data Sheet ADP5071 ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE Parameter Rating
θJA and ΨJT are based on a 4-layer printed circuit board (PCB) PVIN1, PVIN2, PVINSYS −0.3 V to +18 V (two signal and two power planes) with nine thermal vias INBK −0.3 V to PVIN1 + 0.3 V connecting the exposed pad to the ground plane as recommended SW1 −0.3 V to +40 V in the Layout Considerations section. θJC is measured at the top SW2 PVIN2 − 40 V to PVIN2 + 0.3 V of the package and is independent of the PCB. The ΨJT value is PGND, AGND −0.3 V to +0.3 V more appropriate for calculating junction to case temperature in VREG −0.3 V to lower of PVINSYS + the application. 0.3 V or +6 V EN1, EN2, FB1, FB2, SYNC/FREQ −0.3 V to +6 V
Table 4. Thermal Resistance
COMP1, COMP2, SLEW, SS, −0.3 V to VREG + 0.3 V
Package Type θJA θJC ΨJT Unit
SEQ, VREF 20-Lead LFCSP 60.2 36.5 0.63 °C/W Operating Junction −40°C to +125°C 20-Lead TSSOP 58.5 35.0 0.60 °C/W Temperature Range Storage Temperature Range −65°C to +150°C Soldering Conditions JEDEC J-STD-020
ESD CAUTION
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 5 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide
Data Sheet ADP5071 ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE Parameter Rating
θJA and ΨJT are based on a 4-layer printed circuit board (PCB) PVIN1, PVIN2, PVINSYS −0.3 V to +18 V (two signal and two power planes) with nine thermal vias INBK −0.3 V to PVIN1 + 0.3 V connecting the exposed pad to the ground plane as recommended SW1 −0.3 V to +40 V in the Layout Considerations section. θJC is measured at the top SW2 PVIN2 − 40 V to PVIN2 + 0.3 V of the package and is independent of the PCB. The ΨJT value is PGND, AGND −0.3 V to +0.3 V more appropriate for calculating junction to case temperature in VREG −0.3 V to lower of PVINSYS + the application. 0.3 V or +6 V EN1, EN2, FB1, FB2, SYNC/FREQ −0.3 V to +6 V
Table 4. Thermal Resistance
COMP1, COMP2, SLEW, SS, −0.3 V to VREG + 0.3 V
Package Type θJA θJC ΨJT Unit
SEQ, VREF 20-Lead LFCSP 60.2 36.5 0.63 °C/W Operating Junction −40°C to +125°C 20-Lead TSSOP 58.5 35.0 0.60 °C/W Temperature Range Storage Temperature Range −65°C to +150°C Soldering Conditions JEDEC J-STD-020
ESD CAUTION
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 5 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide