Datasheet ADP5070 (Analog Devices) - 6

ADP5070 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2 SYS PGND 1 20 SW2 1 ND 2 N N G SW P SW PVI PVI SW1 2 19 PVIN2 20 19 18 17 16 INBK 3 18 PVINSYS SYNC/FREQ 4 17 PVIN1 INBK 1 15 PVIN1 ADP5070 SYNC/FREQ 2 14 VREG SEQ 5 16 VREG ADP5070 TOP VIEW SEQ 3 13 AGND TOP VIEW SLEW 6 15 AGND SLEW 4 (Not to Scale) 12 VREF FB1 5 11 FB1 FB2 7 14 VREF COMP1 8 13 FB2 6 7 8 9 10 EN1 9 12 COMP2 N1 SS N2 MP1 E E MP2 SS 10 11 EN2 O O
050
C C
002
NOTES
12068-
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND. NOTES
12068-
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
Figure 2. 20-Lead LFCSP Pin Configuration Figure 3. 20-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description
1 3 INBK Input Disconnect Switch Output for the Boost Regulator. 2 4 SYNC/FREQ Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency, connect the SYNC/FREQ pin to an external clock. 3 5 SEQ Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, leave the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to VREG (the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence; hold the other enable pin low. 4 6 SLEW Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest slew rate (best efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to AGND. 5 7 FB1 Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost regulator output capacitor and AGND to program the output voltage. 6 8 COMP1 Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin and AGND. 7 9 EN1 Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the boost regulator output. 8 10 SS Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start time, connect a resistor between the SS pin and AGND. 9 11 EN2 Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable the inverting regulator output. 10 12 COMP2 Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and AGND. 11 13 FB2 Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting regulator output capacitor and VREF to program the output voltage. 12 14 VREF Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and AGND. 13 15 AGND Analog Ground. 14 16 VREG Internal Regulator Output. Connect a 1.0 µF ceramic filter capacitor between the VREG pin and AGND. 15 17 PVIN1 Power Input for the Boost Regulator. 16 18 PVINSYS System Power Supply for the ADP5070. 17 19 PVIN2 Power Input for the Inverting Regulator. Rev. D | Page 6 of 27 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATORS PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN START-UP SEQUENCE APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL COMPONENT SELECTION Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS SUPER LOW NOISE WITH OPTIONAL LDOS SEPIC STEP-UP/STEP-DOWN OPERATION LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE