Datasheet ADP5075 (Analog Devices) - 5

link to page 18 link to page 18
Data Sheet ADP5075 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating
θJA is based on a 4-layer printed circuit board (PCB) (two PVIN, AVIN −0.3 V to +18 V signals and two power planes) as recommended in the Layout SW PVIN − 40 V to PVIN + 0.3 V Considerations section. θJC is measured at the top of the GND −0.3 V to +0.3 V package and is independent of the PCB. VREG −0.3 V to lower of AVIN + 0.3 V or +6 V
Table 4. Thermal Resistance
EN, FB, SYNC/FREQ −0.3 V to +6 V
Package Type θJA θJC Unit
COMP, SLEW, SS, VREF −0.3 V to VREG + 0.3 V 12-Ball WLCSP 68.3 1.2 °C/W Operating Junction −40°C to +125°C Temperature Range Storage Temperature −65°C to +150°C
ESD CAUTION
Range Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 5 of 19 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATORS PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL COMPONENT SELECTION Feedback Resistors Output Capacitor Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection Loop Compensation COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE