Datasheet LTM8049 (Analog Devices) - 7

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TYPICAL PERFORMANCE CHARACTERISTICS Output Ripple, DC2244A Board CLKOUT2 Duty Cycle 800mA Load, 12VIN vs Temperature Measured Across C5, C6
80 fSW = 1MHz 12VOUT 50mV/DIV 60 Y CYCLE (%) –12VOUT 20mV/DIV DUT 40 500ns/DIV 8049 G29 20–50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 8049 G28
PIN FUNCTIONS GND (Bank 1):
Tie these GND pins to a local ground plane
RUN1, RUN2 (Pins B7, K7):
These pins are used to enable/ below the LTM8049 and the circuit components. GND disable the chip and restart the soft-start sequence. Drive MUST BE CONNECTED EITHER TO VOUTP OR VOUTN FOR below 1.21V to stop the LTM8049 from switching. Drive PROPER OPERATION. In most applications, the bulk of above 1.4V to activate the device and restart the soft-start the heat flow out of the LTM8049 is through these pads, sequence. Do not float this pin. so the printed circuit design has a large impact on the
RT1, RT2 (Pins E7, G7):
The RTn pins are used to pro- thermal performance of the part. See the PCB Layout and gram the switching frequency of the LTM8049 by con- Thermal Considerations sections for more details. Return necting a resistor from this pin to ground. The switching the feedback divider (RFB) to this net. frequency of the LTM8049 is determined by the equation
VIN1, VIN2 (Banks 2, 3):
The VINn pins supply current RTn = (81.6/fOSC)-1, where the fOSC is the switching fre- to the LTM8049’s internal regulator and to the internal quency in MHz. This pin must have a resistor to GND. Do power switch. This pin must be locally bypassed with an not apply a voltage to this pin. external, low ESR capacitor.
SS1, SS2 (Pins C7, J7):
Connect a soft-start capacitor
VOUT1P, VOUT2P (Banks 4, 5):
VOUTnP is the positive out- from this pin to GND. Upon start-up, the SSn pins will be put of the LTM8049. Apply an external capacitor between charged by an internal current source to about 2V. VOUTnP and VOUTnN. Tie this net to GND to configure the
SYNC1, SYNC2 (Pins D7, H7):
To synchronize the switch- LMT8049 as a negative output Inverting regulator. ing frequency to an outside clock, simply drive this pin
VOUT1N, VOUT2N (Banks 6, 7):
VOUTnN is the negative out- with a clock signal. The high voltage level of the clock put of the LTM8049. Apply an external capacitor between needs to exceed 1.3V, and the low level must be less VOUTnP and VOUTnN. Tie this net to GND to configure the than 0.4V. Drive this pin to less than 0.4V to revert to the LTM8049 as a positive output SEPIC regulator. internal free running clock. Ground these pins if synchro- nization is not required. See the Applications Information section for more information. Rev B For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package Photo Revision History Typical Application Related Parts