Datasheet MB85AS8MT (Fujitsu) - 10
| Fabricante | Fujitsu |
| Descripción | Memory ReRAM 8M (1024 K x 8) Bit SPI |
| Páginas / Página | 31 / 10 — MB85AS8MT. READ. WRITE |
| Formato / tamaño de archivo | PDF / 1.6 Mb |
| Idioma del documento | Inglés |
MB85AS8MT. READ. WRITE
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MB85AS8MT READ
The READ command reads ReRAM memory cell array data. Arbitrary 24 bits address and op-code of READ are input to SI. The 4-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by con- tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK OP-CODE 24-bit Address SI 0 0 0 0 0 0 1 1 X X X X 19 18 17 16 5 4 3 2 1 0 Invalid MSB LSB MSB Data Out High-Z LSB SO 7 6 5 4 3 2 1 0 Invalid
WRITE
The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address and 8 bits of writing data are input to SI. The 4-bit upper address bit is invalid. During the CS is low, input writing data are temporary saved in the data register. The maximum writing data size is 256 bytes during this CS = low period. If the input writing data are more than 8 bits, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued up to 256 bytes (which is the size of data register). Data exceed 256 bytes can not be written. After rising edge of CS, MB85AS8MT starts writing operation to nonvolatile memory and set WIP bit in status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR command is executable for WIP polling during this writing process, any other commands will not be performed. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK OP-CODE 24-bit Address Data In SI 0 0 0 0 0 0 1 0 X X X X 19 18 17 16 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB LSB MSB LSB High-Z SO 10 DS501-00060-1v0-E Document Outline DESCRIPTION FEATURES PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS BLOCK DIAGRAM SPI MODE SERIAL PERIPHERAL INTERFACE (SPI) STATUS REGISTER OP-CODE COMMAND WRITING OPERATION OF NONVOLATILE MEMORY 1. Address counter control 2. WIP polling BLOCK PROTECT WRITING PROTECT HOLD OPERATION (available only for SOP package) ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS 1. DC Characteristics 2. AC Characteristics 3. Pin Capacitance TIMING DIAGRAM POWER ON/OFF SEQUENCE ReRAM CHARACTERISTICS ESD AND LATCH-UP MB85AS8MTPF (8-pin plastic SOP) REFLOW CONDITIONS AND FLOOR LIFE CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES ORDERING INFORMATION PACKAGE DIMENSION MARKING (11-pin WLP) MARKING (8-pin SOP) PACKING FIGURE 1. Emboss carrier tape and package direction of storage 2. Reel EMBOSS CARRIER TAPE DRAWING
The READ command reads ReRAM memory cell array data. Arbitrary 24 bits address and op-code of READ are input to SI. The 4-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by con- tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK OP-CODE 24-bit Address SI 0 0 0 0 0 0 1 1 X X X X 19 18 17 16 5 4 3 2 1 0 Invalid MSB LSB MSB Data Out High-Z LSB SO 7 6 5 4 3 2 1 0 Invalid
WRITE
The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address and 8 bits of writing data are input to SI. The 4-bit upper address bit is invalid. During the CS is low, input writing data are temporary saved in the data register. The maximum writing data size is 256 bytes during this CS = low period. If the input writing data are more than 8 bits, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued up to 256 bytes (which is the size of data register). Data exceed 256 bytes can not be written. After rising edge of CS, MB85AS8MT starts writing operation to nonvolatile memory and set WIP bit in status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR command is executable for WIP polling during this writing process, any other commands will not be performed. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK OP-CODE 24-bit Address Data In SI 0 0 0 0 0 0 1 0 X X X X 19 18 17 16 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB LSB MSB LSB High-Z SO 10 DS501-00060-1v0-E Document Outline DESCRIPTION FEATURES PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS BLOCK DIAGRAM SPI MODE SERIAL PERIPHERAL INTERFACE (SPI) STATUS REGISTER OP-CODE COMMAND WRITING OPERATION OF NONVOLATILE MEMORY 1. Address counter control 2. WIP polling BLOCK PROTECT WRITING PROTECT HOLD OPERATION (available only for SOP package) ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS 1. DC Characteristics 2. AC Characteristics 3. Pin Capacitance TIMING DIAGRAM POWER ON/OFF SEQUENCE ReRAM CHARACTERISTICS ESD AND LATCH-UP MB85AS8MTPF (8-pin plastic SOP) REFLOW CONDITIONS AND FLOOR LIFE CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES ORDERING INFORMATION PACKAGE DIMENSION MARKING (11-pin WLP) MARKING (8-pin SOP) PACKING FIGURE 1. Emboss carrier tape and package direction of storage 2. Reel EMBOSS CARRIER TAPE DRAWING