Datasheet AP3917D (Diodes) - 7

AP3917D Performance Characteristics
(continued) The value of R4 can be determined by the following equation: V  V O BP _ R 4 HVON  I BP2
Constant Voltage Operation
The AP3917D can be used in a buck circuit as shown in the typical application circuit. In the beginning of each cycle, the internal integrated MOSFET turns ON when the FB voltages fall below the reference voltage VFB (2.5V). The FB voltage is derived from the sampling capacitor
T
voltage, which can reflect output voltage.
C U D
The ON period time is determined by the inductor current variable value IL, (IL is the gap of the peak-current limitation value IPK and the initial
O
inductor current value IINI), the inductance value, and the input voltage. The ON time calculation is as follows:
R P
I  I  I L PK INI t  L   L  ON V V
W
IN _ DC IN _ DC
E
Where I is zero in DCM status.
N
INI When the inductor current reaches peak-current limitation, the internal MOSFET will turn off. The inductor current charges the sampling capacitor (C3) and the output capacitor (C4) via the freewheeling diodes D2 and D3 respectively. In this stage, the sampling capacitor voltage reflects the output voltage. The output voltage can be regulated by sampling the FB voltage. In the MOSFET OFF time, the inductor current decreases linearly from peak current. When the inductor current falls below the output current, the FB voltage begins to decrease with the sampling capacitor voltage decreasing. Once the FB voltage is detected below the reference voltage of primary MOSFET turn-on threshold, a new switching cycle starts. The regulated output voltage can be described as the following equation: R  R V  V  ( 1 2 ) O FB R2 Figures 3(a) and 3(b) show the operation diagram under DCM and CCM. Driver Driver I IPK LIMIT O I I INDUCTANCE INDUCTANCE IO IPK LIMIT V V O O V VFB_SAMPLE V FB_SAMPLE V FB=2.5V FB=2.5V Figure 3(a). DCM Figure 3(b).CCM
Startup Control
A three-stage control method is designed for soft start function. During startup period, the minimum OFF time limit changes from 62µs to 31µs, and then from 31µs to 15.5µs. Every stage has 128 switching cycles (see Figure 4). AP3917D 7 of 12 June 2019 Document number: DS41540 Rev. 4 - 2
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