Datasheet 5X2503 (IDT)

MicroClock Programmable Clock 5X2503 Generator Datasheet Description Features
The 5X2503 MicroClock is a programmable clock generator and is ▪ Configurable OE1 pin function as OE, PPS or DFC control intended for low-power, consumer, wearable and smart devices. function The 5X2503 device is a 3 PLL architecture design. Each PLL is ▪ PPS: Proactive Power Saving features save power during the end individually programmable, al owing for up to 3 unique frequency device power-down mode outputs. The 5X2503 has built-in unique features such as Proactive ▪ DFC: Dynamic Frequency Control feature allows programming up Power Saving (PPS) to deliver better system-level power to 4 difference frequencies that switch dynamical y management. ▪ Integrated 26MHz crystal; no external input source requirement An internal OTP memory al ows the user to store the configuration in ▪ Spread spectrum clock support to lower system EMI the device without programming after power up. It can then be ▪ I2C Interface reprogrammed again through the I2C interface. The device has programmable VCO and PLL source selection
Output Features
allowing the user to do power-performance optimization based on ▪ 3 LVCMOS outputs, 1MHz–125MHz the application requirements. A low-power 32.768kHz clock is ▪ Low-power 32.768kHz clock supported supported with only less than 2μA current consumption for system RTC reference clock needs. ▪ Wireless clock crystal integration and fan-out directly
Typical Applications Key Specifications
▪ SmartDevice, Handheld, Wearable applications ▪ 2μA operation for RTC clock 32.768kHz output ▪ Consumer application crystal replacement ▪ 2.5 × 2.5 mm 12-DFN with crystal integration; small-form-factor package
Block Diagram
Power Monitor VDD1_8 OE1 POR VSS PLL1 OUT1 VDDOUT1 OSC VSS Mux PLL2 OUT2 & Divider VDDOUT2 Calibration VSS PLL3 OUT3 32.768K DCO SEL_DFC/ SCL_DFC1/OE3 Overshoot Reduction I2C Engine Dynamic Frequency Control Logic (DFC) (ORT) SDA_DFC0/OE2 OTP memory (1 configuration ) Proactive Power Saving Logic (PPS) ©2017 Integrated Device Technology, Inc 1 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History