Datasheet VIPER26K (STMicroelectronics) - 4

Pin setting VIPER26K 1 Pin setting Figure 2. Connection diagram Table 1. Pin description SO16 Name Function N Ground.
Connected to the source of the internal power MOSFET and 1 GND controller ground reference.
Not internally connected.
It can be connected to GND (pin 1) or left 2, 3 N.C floating.
Not available for user.
This pin is mechanically connected to the controller 4 N.A. die pad of the frame. It is highly recommended to connect it to GND (pin 1).
Supply voltage of the control section.
This pin provides the charging 5 VDD current of the external capacitor.
Not available for user.
It is highly recommended to connect it to GND (pin 6 N.C. 1).
Inverting input of the internal trans-conductance error amplifier.
Connecting the converter output to this pin through a single resistor results 7 FB in an output voltage equal to the error amplifier reference voltage. An external resistors divider is required for higher output voltages.
Output of the internal trans conductance error amplifier.
The compensation network has to be placed between this pin and GND to 8 COMP achieve stability and good dynamic performance of the voltage control loop. The pin is used also to directly control the PWM with an optocoupler. The linear voltage range extends from VCOMPL to VCOMPH. 9-12 N.C.
Not internally connected.
It has to be left floating.
High voltage drain pin.
The built-in high voltage switched start-up bias 13-16 DRAIN current is drawn from this pin too. Pins connected to the metal frame to facilitate heat dissipation. 4/28 DS12978 Rev 1 Document Outline Figure 1. Basic application schematic 1 Pin setting Figure 2. Connection diagram Table 1. Pin description 2 Electrical and thermal ratings Table 2. Absolute maximum ratings Table 3. Thermal data Figure 3. RthJA Table 4. Avalanche characteristics 3 Electrical characteristics Table 5. Power section Table 6. Supply section Table 7. Controller section 3.1 Typical electrical characteristics Figure 4. IDLIM vs. Tj Figure 5. FOSC vs. Tj Figure 6. VHV_START vs. Tj Figure 7. VREF_FB vs. Tj Figure 8. IDD0 vs. Tj Figure 9. IDD1 vs. Tj Figure 10. GM vs. Tj Figure 11. HCOMP vs. Tj Figure 12. ICOMP(source/sink) vs. Tj Figure 13. ICOMP(max source) vs. Tj Figure 14. Power MOSFET capacitances variation vs. VDS @ VGS=0, f=1MHz Figure 15. VBVDSS vs. TJ .. Figure 16. RDS(on) vs. Tj Figure 17. Maximum avalanche energy vs. Tj Figure 18. SOA SSOP10 package 4 General description 4.1 Block diagram Figure 19. Block diagram 4.2 Typical power capability Table 8. Typical power 4.3 Primary MOSFET 4.4 High voltage startup Figure 20. Timing diagram: normal power-up and power-down sequences 4.5 Oscillator 4.6 Soft-start 4.7 Current limit set point 4.8 FB pin and COMP pin Figure 21. Feedback circuit Figure 22. COMP pin vs. IDLIM 4.9 Burst mode Figure 23. Load-dependent operating modes: timing diagram 4.10 Automatic auto restart after overload or short-circuit Figure 24. Timing diagram: OLP sequence 4.11 Open loop failure protection 4.12 Thermal shutdown Figure 25. Timing diagram: OLP sequence 5 Application information Figure 26. Typical isolated flyback configuration with secondary regulation Figure 27. Typical isolated flyback configuration with primary regulation Figure 28. Typical non isolated flyback configuration Figure 29. Ultra wide range Buck configuration 5.1 Layout guidelines and design recommendations Figure 30. Recommended routing for flyback converter Figure 31. Recommended routing for Buck converter 6 Package information 6.1 SO16N package information Figure 32. SO16N package outline Table 9. SO16N mechanical data 7 Order code Table 10. Order codes 8 Revision history Table 11. Document history