Datasheet NCD2400M (IXYS) - 9
| Fabricante | IXYS |
| Descripción | Wide Capacitance Range, Non-volatileDigital Programmable Capacitor |
| Páginas / Página | 22 / 9 — NCD2400M. Figure 6: Variation of the Capacitance at 10MHz with Supply … |
| Formato / tamaño de archivo | PDF / 414 Kb |
| Idioma del documento | Inglés |
NCD2400M. Figure 6: Variation of the Capacitance at 10MHz with Supply Voltage, Relative to the Value at 3.3V
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INTEGRATED CIRCUITS DIVISION
NCD2400M
The figure below shows how the capacitance varies with the supply voltage while CN is biased at one-half of the supply voltage level. Here, the value obtained for 3.3V is used as a reference and the deviation is given in percentage. Please note that for VDD > 3.6V no further variations are expected.
Figure 6: Variation of the Capacitance at 10MHz with Supply Voltage, Relative to the Value at 3.3V Capacitance Variation vs. Supply Voltage Relative to 3.3V (f=10MHz)
4.0 C0 3.5 C1 C2
(%)
3.0 C4 C 2.5 8 C16 2.0 C32 C
ariation
1.5 64 C128 C 1.0 256 C511 0.5 0.0 -0.5
Capacitance V
-1.0 -1.5 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
DC voltage biasing of the CN terminal has a small though visible influence on the performance of the Digital Programmable Capacitor. The table below presents the variation of the series capacitance and ESR at 10MHz when pin CN is biased at 0V, 1.65V and 3.3V, with VDD=3.3V. DC bias applied to pin CP has no affect on the capacitance or ESR values.
Capacitance (pF) ESR ( ) Code / Vbias (V) 0 1.65 3.3 0 1.65 3.3
0 1.7 1.7 1.9 0.509 0.442 0.695 1 2.1 2.1 2.3 0.739 0.720 1.006 2 2.5 2.5 2.7 0.949 0.973 1.29 4 3.2 3.2 3.5 1.271 1.366 1.742 8 4.7 4.7 5.1 1.754 1.952 2.431 16 7.6 7.7 8.2 2.256 2.564 3.188 32 13.7 13.7 14.3 4.342 4.968 6.31 64 25.6 25.6 26.4 3.259 3.755 4.882 128 49.6 49.6 50.3 2.063 2.372 3.14 256 97.4 97.5 98.1 1.204 1.377 1.827 511 193.2 194 193.2 0.75 0.846 1.106 R01
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9 Document Outline Features Applications Description 1. Specifications 1.1 Package Pinout 1.2 Pin Descriptions 1.3 Absolute Maximum Ratings 1.4 Recommended Operating Conditions 1.5 ESD Rating 1.6 General Conditions for Electrical Characteristics 1.7 Capacitor Electrical Characteristics 1.8 Digital Interface: Electrical Characteristics of SDA and SCL 1.9 Digital Interface: AC Characteristics 1.10 Power Supply 2. Performance Data 3. Functional Description 3.1 Introduction 3.2 Capacitive Digital to Analog Converter (CDAC) 3.3 Non-Volatile Memory Configuration 3.4 Device Address 3.5 Operating Modes 3.5.1 Volatile Mode 3.5.2 Non-Volatile Mode 3.6 I2C Serial Interface 3.6.1 Write Commands 3.6.2 Write Volatile Register Operation 3.6.3 Write Non-Volatile Memory Operation 3.6.4 Read Operation 3.6.5 Set Non-Volatile Mode Operation 3.6.6 Electrical and Timing Considerations 3.6.7 Application Diagrams 3.7 Capacitor Interface Electrical and Biasing Considerations 4. Capacitance Determination and Programming Procedure 5. Manufacturing Information 5.1 Moisture Sensitivity 5.2 ESD Sensitivity 5.3 Soldering Profile 5.4 Board Wash 5.5 Mechanical Dimensions 5.5.1 Package Dimensions 5.5.2 Tape & Reel Specification
NCD2400M
The figure below shows how the capacitance varies with the supply voltage while CN is biased at one-half of the supply voltage level. Here, the value obtained for 3.3V is used as a reference and the deviation is given in percentage. Please note that for VDD > 3.6V no further variations are expected.
Figure 6: Variation of the Capacitance at 10MHz with Supply Voltage, Relative to the Value at 3.3V Capacitance Variation vs. Supply Voltage Relative to 3.3V (f=10MHz)
4.0 C0 3.5 C1 C2
(%)
3.0 C4 C 2.5 8 C16 2.0 C32 C
ariation
1.5 64 C128 C 1.0 256 C511 0.5 0.0 -0.5
Capacitance V
-1.0 -1.5 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
DC voltage biasing of the CN terminal has a small though visible influence on the performance of the Digital Programmable Capacitor. The table below presents the variation of the series capacitance and ESR at 10MHz when pin CN is biased at 0V, 1.65V and 3.3V, with VDD=3.3V. DC bias applied to pin CP has no affect on the capacitance or ESR values.
Capacitance (pF) ESR ( ) Code / Vbias (V) 0 1.65 3.3 0 1.65 3.3
0 1.7 1.7 1.9 0.509 0.442 0.695 1 2.1 2.1 2.3 0.739 0.720 1.006 2 2.5 2.5 2.7 0.949 0.973 1.29 4 3.2 3.2 3.5 1.271 1.366 1.742 8 4.7 4.7 5.1 1.754 1.952 2.431 16 7.6 7.7 8.2 2.256 2.564 3.188 32 13.7 13.7 14.3 4.342 4.968 6.31 64 25.6 25.6 26.4 3.259 3.755 4.882 128 49.6 49.6 50.3 2.063 2.372 3.14 256 97.4 97.5 98.1 1.204 1.377 1.827 511 193.2 194 193.2 0.75 0.846 1.106 R01
www.ixysic.com
9 Document Outline Features Applications Description 1. Specifications 1.1 Package Pinout 1.2 Pin Descriptions 1.3 Absolute Maximum Ratings 1.4 Recommended Operating Conditions 1.5 ESD Rating 1.6 General Conditions for Electrical Characteristics 1.7 Capacitor Electrical Characteristics 1.8 Digital Interface: Electrical Characteristics of SDA and SCL 1.9 Digital Interface: AC Characteristics 1.10 Power Supply 2. Performance Data 3. Functional Description 3.1 Introduction 3.2 Capacitive Digital to Analog Converter (CDAC) 3.3 Non-Volatile Memory Configuration 3.4 Device Address 3.5 Operating Modes 3.5.1 Volatile Mode 3.5.2 Non-Volatile Mode 3.6 I2C Serial Interface 3.6.1 Write Commands 3.6.2 Write Volatile Register Operation 3.6.3 Write Non-Volatile Memory Operation 3.6.4 Read Operation 3.6.5 Set Non-Volatile Mode Operation 3.6.6 Electrical and Timing Considerations 3.6.7 Application Diagrams 3.7 Capacitor Interface Electrical and Biasing Considerations 4. Capacitance Determination and Programming Procedure 5. Manufacturing Information 5.1 Moisture Sensitivity 5.2 ESD Sensitivity 5.3 Soldering Profile 5.4 Board Wash 5.5 Mechanical Dimensions 5.5.1 Package Dimensions 5.5.2 Tape & Reel Specification